BURIED VIA TECHNOLOGY FOR THREE DIMENSIONAL INTEGRATED CIRCUITS

• US 20070170574A1
• Filed: 01/18/2007
• Published: 07/26/2007
• Est. Priority Date: 01/25/2006
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Licensing, LLC
• Inventors: DeNatale, Jeffrey F., Lauxtermann, Stefan C.
• Granted Patent: US 7,671,460 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Claims

1. A three dimensional integrated circuit comprising:

a first active circuit layer deposited on a substrate wafer;

a second active circuit layer coupled to the first active circuit layer, the second active circuit layer having a via and a first metal layer, the first metal layer is embedded in a first dielectric material in the second active circuit layer, the via is etched through the first dielectric material to expose the first metal layer, the via contains metal in contact with the first metal layer of the second active circuit layer; and

a third active circuit layer having a second metal layer, the second metal layer is embedded in a second dielectric material in the third active circuit layer, the second dielectric material has an opening that exposes the second metal layer of the third active circuit layer, the opening is aligned above the via of the second active circuit layer, the opening contains a metal bond that mechanically couples the third active circuit layer to the second active circuit layer and electrically couples the first metal layer of the second active circuit layer to the second metal layer of the third active circuit layer.

2. The three dimensional integrated circuit of claim 1, wherein the second active circuit layer is coupled to the first active circuit layer using a bond material selected from a group consisting of indium, gold and solder.

3. The three dimensional integrated circuit of claim 1, wherein the second active circuit layer is coupled to the first active circuit layer using an under fill.

4. The three dimensional integrated circuit of claim 1, wherein the third active circuit layer is coupled to the second active circuit layer using an under fill.

5. The three dimensional integrated circuit of claim 1, wherein the metal bond is selected from a group consisting of indium, gold and solder.

6. The three dimensional integrated circuit of claim 1, wherein the first active circuit layer is about 5 μ

m thick.

7. The three dimensional integrated circuit of claim 1, wherein the via is about 5 μ

m deep.

8. The three dimensional integrated circuit of claim 1, wherein the via has an aspect ratio less than or equal to 20.

9. The three dimensional integrated circuit of claim 1, wherein the first metal layer and the second metal layer are each about 1 μ

m thick.

10. The three dimensional integrated circuit of claim 1, wherein the second active circuit layer further includes a wafer layer and a buried oxide layer, the via is etched through the buried oxide layer and the wafer layer to expose the first metal layer without penetrating the first metal layer.

11. A three dimensional integrated circuit comprising:

a circuit layer deposited on a substrate wafer;

a first known good die coupled to the circuit layer, the first known good die has a via and a first metal layer, the first metal layer is embedded in a first dielectric material of the first known good die, the via is etched through the first dielectric material to expose the first metal layer, the via contains metal in contact with the first metal layer; and

a second known good die coupled to the first known good die, the second known good die has a second metal layer, the second metal layer is embedded in a second dielectric material of the second known good die, the second dielectric material has an opening that exposes the second metal layer, the opening is aligned above the via of the first known good die, the opening contains a metal bond that mechanically couples the second known good die to the first known good die and electrically couples the first metal layer to the second metal layer.

12. The three dimensional integrated circuit of claim 11, wherein the first known good die is coupled to the circuit layer using a bond material selected from a group consisting of indium, gold and solder.

13. The three dimensional integrated circuit of claim 11, wherein the first known good die is coupled to the first active circuit layer using an under fill.

14. The three dimensional integrated circuit of claim 11, wherein the metal bond is selected from a group consisting of indium, gold and solder.

15. The three dimensional integrated circuit of claim 11, wherein the circuit layer is about 5 μ

m thick.

16. The three dimensional integrated circuit of claim 11, wherein the via is about 5 μ

m deep.

17. The three dimensional integrated circuit of claim 11, wherein the via has an aspect ratio less than or equal to 20.

18. The three dimensional integrated circuit of claim 11, wherein the first metal layer and the second metal layer are each about 1 μ

m thick.

19. The three dimensional integrated circuit of claim 11, wherein the first known good die further includes a wafer layer and a buried oxide layer, the via is etched through the buried oxide layer and the wafer layer to expose the first metal layer.

20. A fabrication method for a three dimensional integrated circuit having a first and a second active circuit layer, the first active circuit layer has a first metal layer inside the first active circuit layer, the second active circuit layer has a second metal layer, the method comprising:

etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer;

depositing metal inside the via, the metal inside the via being in contact with the first metal layer; and

bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

21. The fabrication method of claim 20, wherein the second metal layer is inside the second active circuit layer.

22. The fabrication method of claim 20, further comprising the step of coupling the first active circuit layer to the second active circuit layer using an under fill.

23. The fabrication method of claim 20, wherein the metal bond is selected from a group consisting of indium, gold and solder.

24. The fabrication method of claim 20, wherein the via is about 5 μ

m deep.

25. The fabrication method of claim 20, wherein the via has an aspect ratio less than or equal to 20.

27. The fabrication method of claim 20, wherein the second metal layer is inside the second known good die.

28. The fabrication method of claim 20, further comprising the step of coupling the first known good die to the second known good die using an under fill.

29. The fabrication method of claim 20, wherein the metal bond is selected from a group consisting of indium, gold and solder.

30. The fabrication method of claim 20, wherein the via is about 5 μ

m deep.

31. The fabrication method of claim 20, wherein the via has an aspect ratio less than or equal to 20.

26. A fabrication method for a three dimensional integrated circuit having a first and a second known good die, the first known good die has a first metal layer inside the first known good die, the second known good die has a second metal layer, the method comprising:

etching a via in the first known good die to expose the first metal layer;

depositing metal inside the via, the metal inside the via being in contact with the first metal layer; and

bonding the second known good die to the first known good die using a metal bond that connects the metal inside the via to the second metal layer of the second known good die.

32. A fabrication method for a three dimensional integrated circuit, the method comprising:

placing a first active circuit layer on a first substrate and a second active circuit layer on a second substrate, the first active circuit layer having a first metal layer, a semiconductor substrate layer and a buried oxide layer, the first metal layer is embedded in a first dielectric material, the semiconductor substrate layer separates the buried oxide layer from the first dielectric material, the second active circuit layer having a second metal layer embedded in a second dielectric material;

hybridizing the first active circuit layer to a handling wafer;

etching the first substrate from the first active circuit layer using the buried oxide layer as an etch stop;

etching a via through the buried oxide layer, the semiconductor substrate layer and the first dielectric material to expose the first metal layer in the first active circuit layer without penetrating the first metal layer;

depositing metal inside the via, the metal inside the via being in contact with the first metal layer;

etching an opening in the second dielectric material to expose the second metal layer in the second active circuit layer;

aligning the opening in the second active circuit layer with the via of the first active circuit layer; and

hybridizing the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

33. The fabrication method of claim 32, further comprising the step of coupling the first active circuit layer to the second active circuit layer using an under fill.

34. The fabrication method of claim 32, wherein the metal bond is selected from a group consisting of indium, gold and solder.

35. The fabrication method of claim 32, wherein the via is about 5 μ

m deep.

36. The fabrication method of claim 32, wherein the via has an aspect ratio less than or equal to 20.

37. The fabrication method of claim 32, wherein the first active circuit layer is bonded to the handling wafer using an under fill.

38. The fabrication method of claim 32, wherein the first active circuit layer is bonded to the handling wafer using a metal bond selected from a group consisting of indium, gold and solder.