Multilayer integrated circuit for RF communication and method for assembly thereof

• US 20070170583A1
• Filed: 09/27/2006
• Published: 07/26/2007
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies Korea Co Ltd (Broadcom, Inc.)
• Inventors: Kwon, Youngwoo, Chung, Ki
• Granted Patent: US 7,638,364 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49589 Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

A low profile radio frequency (RF) module and package with efficient heat dissipation characteristics, and a method of assembly thereof, are provided. In some embodiments, the RF module package comprises a radio frequency integrated circuit (RFIC) attached to a recessed area of a lead frame. The RFIC has an active integrated circuit pattern and a plurality of conductors formed on input/output pads of the active integrated circuit pattern. An integrated passive device (IPD) is attached to the RFIC via the plurality of conductors. The IPD has a passive integrated circuit pattern, a plurality of electrode pads connected to nodes of the passive integrated circuit pattern, and metal-filled vias for electrically connecting the electrode pads to the plurality of conductors. The RFIC includes a plurality of heat conducting vias for conducting heat to the lead frame.

Claims

1. A vertically integrated radio frequency module, comprising:

a radio frequency integrated circuit die including, on an upper surface thereof, an active integrated circuit pattern having an input/output pad;

a conductor disposed on the input/output pad; and

an integrated passive device die disposed above the radio frequency integrated circuit die and including, on an upper surface thereof, a passive integrated circuit pattern having an electrode pad electrically connected to the conductor.

2. The radio frequency module of claim 1 wherein the conductor is a stud bump.

3. The radio frequency module of claim 1 wherein the conductor is a solder bump.

4. The radio frequency module of claim 1 wherein the conductor is an electroless bump.

5. The radio frequency module of claim 1 wherein the integrated passive device and the radio frequency integrated circuit dies have a same lateral dimension.

6. The radio frequency module of claim 1 wherein the radio frequency integrated circuit die further includes a via.

7. The radio frequency module of claim 6 wherein the via includes a metal plug.

8. The radio frequency module of claim 7 wherein the via further includes an air space.

9. The radio frequency module of claim 1 wherein the radio frequency integrated circuit die includes gallium arsenide and the integrated passive device die includes silicon.

10. The radio frequency module of claim 1 wherein the integrated passive device die further includes a via.

11. The radio frequency module of claim 10 wherein the via is filled with a metal.

12. The radio frequency module of claim 10 wherein the via is connected to the conductor.

13. A vertically integrated radio frequency module package, comprising:

a lead frame;

a radio frequency integrated circuit die attached to the lead frame and including, on an upper surface thereof, an active integrated circuit pattern having an input/output pad;

a conductor disposed on the input/output pad; and

an integrated passive device die disposed above the radio frequency integrated circuit die and including, on an upper surface thereof, a passive integrated circuit pattern having an electrode pad electrically connected to the conductor.

14. The radio frequency module package of claim 13 wherein the lead frame includes a recessed area.

15. The radio frequency module package of claim 14 wherein the radio frequency integrated circuit die is attached to the lead frame within the recessed area.

16. The radio frequency module package of claim 13 wherein the radio frequency integrated circuit die is attached to the lead frame with a solder paste.

17. The radio frequency module package of claim 13 further comprising a space between the radio frequency integrated circuit and integrated passive device dies.

18. The radio frequency module package of claim 17 wherein the space is filled with an electrically insulating material.

19. The radio frequency module package of claim 13 further comprising a protective material covering the lead frame and the radio frequency integrated circuit and integrated passive device dies.

20. The radio frequency module package of claim 19 wherein the protective material includes a thermosetting material.

21. The radio frequency module package of claim 13 wherein the lead frame includes coupling fingers.

22. The radio frequency module package of claim 21 wherein the coupling fingers are used as external pins.

23. A method of assembling a vertically integrated radio frequency module package, the method comprising:

preparing a first wafer including defining an active integrated circuit pattern;

preparing a second wafer including defining a passive integrated circuit pattern;

simultaneously sawing the first and second wafers to form

from the first wafer a radio frequency integrated circuit die having the active integrated circuit pattern on an upper surface thereof, and

from the second wafer an integrated passive device die having the passive integrated circuit pattern on an upper surface thereof;

attaching the radio frequency integrated circuit die to a lead frame; and

joining a bottom surface of the integrated passive device die to an upper surface of the radio frequency integrated circuit die.

24. The method of claim 23 wherein preparing the first wafer further includes thinning the first wafer.

25. The method of claim 24 wherein thinning the first wafer includes back-grinding the first wafer.

26. The method of claim 23 wherein preparing the first wafer further includes forming a via through the first wafer.

27. The method of claim 26 wherein forming the via includes etching.

28. The method of claim 26 wherein forming the via includes metallizing the via.

29. The method of claim 23 wherein preparing the first wafer further includes forming a conductor on an input/output pad of the active integrated circuit pattern.

30. The method of claim 29 wherein the conductor includes gold.

31. The method of claim 23 wherein preparing the second wafer further includes forming a via through the second wafer.

32. The method of claim 31 wherein forming the via includes metallizing the via.

33. The method of claim 23 wherein attaching the radio frequency integrated circuit die to the lead frame includes thermally curing a solder paste.

34. The method of claim 23 further comprising preparing the lead frame before attaching the radio frequency integrated circuit die thereto.

35. The method of claim 34 wherein preparing the lead frame includes forming a recessed area.

36. The method of claim 35 wherein forming the recessed area includes etching the lead frame.

37. The method of claim 34 wherein attaching the radio frequency integrated circuit die to the lead frame includes attaching the radio frequency integrated circuit die within the recessed area.

38. The method of claim 29 wherein preparing the second wafer further includes forming a metallized via through the second wafer and wherein joining the bottom surface of the integrated passive device die to the upper surface of the radio frequency integrated circuit die includes joining the conductor of the active integrated circuit pattern to the metallized via.

39. The method of claim 23 further comprising disposing an electrically insulating material in a space between the dies.

40. The method of claim 39 wherein disposing the electrically insulating material in the space includes under-filling the space.

41. The method of claim 39 wherein the electrically insulating material includes an epoxy.

42. The method of claim 23 further comprising forming an over-mold over the lead frame and the radio frequency integrated circuit and integrated passive device dies.

43. The method of claim 42 wherein forming the over-mold includes depositing and curing an epoxy.