Current-controlled CMOS logic family
First Claim
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1. A circuit, comprising:
- an input that is operable to receive an input signal;
a deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to convert the input signal into a parallel signal that includes a plurality of signals such that the plurality of signals includes all information within the input signal; and
an output that is operable to transmit the parallel signal by transmitting each signal of the plurality of signals.
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Abstract
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
25 Citations
20 Claims
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1. A circuit, comprising:
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an input that is operable to receive an input signal;
a deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to convert the input signal into a parallel signal that includes a plurality of signals such that the plurality of signals includes all information within the input signal; and
an output that is operable to transmit the parallel signal by transmitting each signal of the plurality of signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit, comprising:
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an input that is operable to receive a parallel input signal that includes a plurality of input signals;
a serializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and convert the plurality of input signals of the parallel input signal into a serial output signal such that the serial output signal includes all information within the parallel input signal; and
an output that is operable to transmit serial output signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A circuit, comprising:
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an input that is operable to receive a serial input signal;
a deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to convert the serial input signal into a parallel signal that includes a plurality of input signals such that the plurality of input signals includes all information within the serial input signal;
a core processing circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the parallel signal thereby generating a processed parallel signal;
a serializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive the processed parallel signal and to convert the processed parallel signal into a serial output signal such that the serial output signal includes all information within the processed parallel signal; and
an output that is operable to transmit the serial output signal. - View Dependent Claims (18, 19, 20)
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Specification