Semiconductor device with electrically broken fuse and its manufacture method

• US 20070171691A1
• Filed: 07/31/2006
• Published: 07/26/2007
• Est. Priority Date: 01/24/2006
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Ashizawa, Tetsuo
• Granted Patent: US 7,292,493 B1
• Time in Patent Office: Days
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/80 with improved layout

Abstract

An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor including a source region, a drain region and a gate electrode. The source and drain regions sandwiches a channel region. The gate electrode controls a conduction state between the source and drain regions. The drain region is connected to one end of the electric fuse. A breaker pad is connected to the end of the electric fuse to supply a fusing current to the electric fuse. A back-bias pad applies a fixed voltage to the first surface layer independently from both a power supply voltage and a ground potential. A fuse information read circuit reads a breakdown/non-breakdown state of the electric fuse.

Claims

1. A semiconductor device comprising:

a first electric fuse formed over a semiconductor substrate, the first electric fuse being broken when a current floes therethrough;

a first breaker transistor including a source region, a drain region and a gate electrode, the source region and the drain region being disposed in a first surface layer of the semiconductor substrate of a first conductivity type and sandwiching a channel region, the gate electrode controlling a conduction state between the source and drain regions, the drain region being connected to one end of the first electric fuse;

a breaker pad connected to another end of the first electric fuse for supplying a fusing current to the first electric fuse;

a back-bias pad capable of applying a fixed voltage to the first surface layer independently from both a power supply voltage and a ground potential; and

a first fuse information read circuit for reading a breakdown/non-breakdown state of the first electric fuse.

2. The semiconductor device according to claim 1, further comprising:

another first transistor disposed in the first surface layer;

a first well contact disposed in the first surface layer for applying a fixed potential to the first surface layer; and

a back-bias well contact disposed in the first surface layer and connected to the back-bias pad.

3. The semiconductor device according to claim 1, wherein:

a plurality of well contacts are distributed under a condition that as a unit area is defined as a standard size square, the unit area is superposed on or contacts at least one well contact no matter where the unit area is disposed in a well formed in a surface layer of the semiconductor substrate; and

under a condition that other well contacts for applying a same fixed potential as the fixed potential to be applied by the first well contact are disposed in the first surface layer wherein the other well contacts for applying the fixed potential are permitted to be disposed at a distance shorter than a side length of the unit area, and the back-bias well contact and the other well contacts are prohibited to be disposed at a distance shorter than the side length of the unit area, the back-bias well contact, the first well contact and the other well contacts are distributed.

4. The semiconductor device according to claim 1, further comprising:

a first read transistor for connecting one end of the first electric fuse to the ground potential;

a second read transistor for connecting another end of the first electric fuse to the first fuse information read circuit, the first surface layer containing the first breaker transistor consists of a first well;

a second well containing the first and second read transistors;

a back-bias well contact disposed in the first well and connected to the back-bias pad; and

a first well contact disposed in the second well for applying a fixed potential to the second well, the first and second wells being electrically isolated.

5. The semiconductor device according to claim 1, further comprising:

a plurality of other second electric fuses formed over the semiconductor substrate, the second electric fuse being broken when a current flows therethrough;

a second breaker transistor disposed in the first surface layer for each of the second electric fuses, the second breaker transistor including a source region, a drain region and a gate electrode, the source region and the drain region sandwiching a channel region, the gate electrode controlling a conduction state between the source and drain regions, the drain region being connected to one end of the corresponding second electric fuse; and

a second fuse information read circuit disposed for each second electric fuse for reading a breakdown/non-breakdown state of a corresponding second electric fuse,

wherein the breaker pad is connected to another end of the second electric fuse.

6. A semiconductor device comprising:

a first RAM macro disposed over a semiconductor substrate and having a redundancy structure;

a first redundancy information memory circuit for supplying redundancy retrieval information to the first RAM macro;

a breaker pad; and

a back-bias pad,

wherein;

the first redundancy information memory circuit includes a plurality of fuse blocks, each of the fuse blocks comprising;

an electric fuse formed over the semiconductor substrate, the electric fuse being broken when a current flows therethrough;

a breaker transistor disposed in a first surface layer of the semiconductor substrate of a first conductivity type for each electric fuse, the breaker transistor including a source region, a drain region and a gate electrode, the source region and the drain region sandwiching a channel region, the gate electrode controlling a conduction state between the source and drain regions, the drain region being connected to one end of the corresponding electric fuse; and

a fuse information read circuit disposed for each electric fuse for reading a breakdown/non-breakdown state of the corresponding electric fuse;

the breaker pad is connected to another end of the electric fuses for supplying a fusing current to the electric fuses; and

the back-bias pad being capable of applying a fixed voltage to the first surface layer independently from a power supply voltage and a ground potential.

7. The semiconductor device according to claim 6, further comprising:

at least one second RAM macro having a redundancy structure and disposed over the semiconductor substrate; and

a second redundancy information memory circuit for supplying redundancy retrieval information to the second RAM macro,

wherein the second redundancy information memory circuit includes a plurality of fuse blocks, each of the fuse blocks comprising;

an electric fuse formed over the semiconductor substrate, the electric fuse being broken when a current flows therethrough;

a breaker transistor disposed in the first surface layer of the semiconductor substrate of the first conductivity type for each electric fuse, the breaker transistor including a source region, a drain region a d a gate electrode, the source region and the drain region sandwiching a channel region, the gate electrode controlling a conduction state between the source and drain regions, the drain region being connected to one end of the electric fuse; and

a fuse information read circuit disposed for each electric fuse for reading a breakdown/non-breakdown state of the corresponding electric fuse, and

wherein the first and second redundancy information memory circuits are disposed adjacent to each other.

8. The semiconductor device according to claim 6, wherein the breaker transistors in the fuse blocks are disposed in a same well of the first conductivity type.

9. A manufacture method for a semiconductor device comprising:

an electric fuse formed on a semiconductor substrate, the first electric fuse being broken when a current flows therethrough; and

a breaker transistor including a source region, a drain region and a gate electrode, the source region and the drain region being disposed in a first surface layer of the semiconductor substrate of a first conductivity type and sandwiching a channel region, the gate electrode controlling a conduction state between the source and drain regions, the drain region being connected to one end of the electric fuse,

and the manufacture method comprising a step of;

applying a back-bias to the first surface layer so that a forward voltage is applied across a pn-junction between the first surface layer and the source region, applying a gate voltage to the gate electrode so that the breaker transistor turns on, and in this state, applying a fusing current to a serial circuit of the electric fuse and the breaker transistor to break the electric fuse.

10. The manufacture method for a semiconductor device according to claim 9, wherein a voltage applied across the pn-junction between the first surface layer and the source region by the back-bias is at most a threshold voltage, at which a forward current starts flowing across the pn-junction between the first surface layer and the source region.