Dynamic matching of signal path and reference path for sensing

• US 20070171717A1
• Filed: 07/19/2006
• Published: 07/26/2007
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Sofer, Yair, Betser, Yoram, Maayan, Eduardo
• Granted Patent: US 7,466,594 B2
• Time in Patent Office: Days
• US Class Current: 365/185.130
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.

Claims

1. A method for operating a non-volatile memory cell device, the method comprising:

providing an array of memory array cells connected to word lines and local bit lines, said local bit lines being connected to global bit lines via select transistors, said array being divided into isolated sectors;

providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX (Y multiplexer);

providing a reference cell located in a reference mini-array, said reference cell being connected to said YMUX and being connected to said sense amplifier via another sensing path;

driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via said YMUX through accessed global bit lines; and

matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier.

2. The method according to claim 1, wherein the non-accessed global bit line is dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.

3. The method according to claim 1, further comprising matching a coupling signal between the drain and source sides of the memory array cell and the reference cell by using a neighboring, non-accessed global bit line as the reference global bit line.

4. The method according to claim 3, wherein capacitances of the sensing path of the memory array cell and of the sensing path of the reference cell are fully matched.

5. The method according to claim 1, wherein the sensing comprises source side sensing, wherein said sense amplifier senses the source sides of the memory array cells, the accessed global bit line serving as a global source bit line, and wherein said common bit line (BL) driver drives drain sides of the memory array cells and the reference cells through the accessed global bit lines serving as global drain bit lines.

6. The method according to claim 1, wherein the memory array cells and the reference cell comprise dual bit cells, each having a right side bit and a left side bit.

7. The method according to claim 6, wherein sensing a bit of one of the memory array cells comprises:

using the local bit line to which a first side of the memory array cell is connected as the local drain bit line, and the local bit line to which a second side of the memory array cell is connected as the local source bit line;

connecting the local drain bit line via one of the select transistors to a global bit line, this global bit line becoming the drain global bit line, and connecting the local source bit line via another of the select transistors to another global bit line, this global bit line becoming the source global bit line;

connecting the drain global bit line to a reference drain bit line via a ref-select transistor, the drain side of the reference cell of the reference mini-array being connected to the reference drain bit line;

connecting another global bit line which is adjacent to the drain global bit line on the opposite side from the source global bit line to a reference source bit line via another ref-select transistor, the source side of the reference cell of the reference mini-array being connected to the reference source bit line; and

blocking the global bit line, which is connected to the reference source bit line, from being connected to the array of memory array cells.