Memory and method for sensing data in a memory using complementary sensing scheme

• US 20070171747A1
• Filed: 01/23/2006
• Published: 07/26/2007
• Est. Priority Date: 01/23/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhang, Shayan, Hunter, Bradford
• Granted Patent: US 8,077,533 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

Claims

1. A method for sensing data in a memory comprising:

precharging a local data line pair to a first logic state and a global data line pair to a second logic state;

coupling a selected memory cell to said local data line pair to develop a differential local data line voltage;

subsequently amplifying said differential local data line voltage to form an amplified differential local data line voltage; and

driving a selected one of said global data line pair to said first logic state in response to said amplified differential local data line voltage to form a differential global data line voltage.

2. The method of claim 1 further comprising:

subsequently amplifying said differential global data line voltage to form an amplified differential global data line voltage.

3. The method of claim 2 further comprising:

outputting a data output signal in response to said amplified differential global data line voltage.

4. The method of claim 3 wherein said outputting further comprises:

outputting said data output signal in response to a voltage on a predetermined global data line of said global data line pair.

5. The method of claim 2 wherein said subsequently amplifying said differential global data line voltage comprises:

subsequently amplifying said differential global data line voltage while continuing to amplify said differential local data line voltage, and continuing to amplify said global data line voltage while ceasing to amplify said differential local data line voltage.

6. The method of claim 2 wherein said subsequently amplifying said differential global data line voltage further comprises:

subsequently activating a global sense amplifier after a programmable delay determined in response to a state of at least one fuse.

7. The method of claim 1 wherein said precharging comprises:

precharging said local data line pair to a logic high state and said global data line pair to a logic low state.

8. The method of claim 1 wherein said subsequently amplifying said differential local data line voltage comprises:

subsequently activating a local sense amplifier after a first programmable delay determined in response to a state of at least one fuse.

9. The method of claim 8 further comprising:

subsequently activating a global sense amplifier after a second programmable delay determined in response to a state of at least one other fuse.

10. The method of claim 1 wherein said subsequently amplifying said differential local data line voltage comprises:

subsequently activating a selected local sense amplifier of a plurality of local sense amplifiers.

11. A method for accessing data in a memory comprising:

precharging a local data line pair to a first logic state;

during a first time period, coupling a memory cell to said local data line pair, and precharging a global data line pair to a second logic state;

during a subsequent second time period, amplifying a difference in voltage between first and second local data lines of said local data line pair, driving a selected global data line of said global data line pair to said first logic state in response to a sensed voltage on said local data line pair, and amplifying a difference in voltage between first and second global data lines of said global data line pair; and

during a subsequent third time period, latching said difference in voltage between said first and second global data lines of said global data line pair, and precharging said local data line pair to said first logic state in preparation for a subsequent access.

12. The method of claim 11, further comprising the step of:

starting to amplify said difference in voltage between said first and second global data lines of said global data line pair a first programmable delay time after starting to amplify said difference in voltage between said first and second local data lines of said local data line pair.

13. The method of claim 11 wherein said latching comprises:

keeping a global sense amplifier active, thereby holding said difference in voltage between said first and second global data lines of said global data line pair.

14. The method of claim 11 wherein coupling said memory cell to said local data line pair comprises:

coupling a bit line pair to which said memory cell is coupled to said local data line pair.

15. A memory comprising:

a local data line pair;

a local data line precharge circuit coupled to said local data line pair and to a first voltage representative of a first logic state;

a local sense amplifier coupled to said local data line pair and active in response to a first control signal;

a global data line pair;

a global data line precharge circuit coupled to said global data line pair and to a second voltage representative of a second logic state;

a driver circuit having inputs coupled to said local data line pair and to said first voltage, and outputs coupled to said global data line pair;

a global sense amplifier coupled to said global data lines and active in response to a second control signal; and

a control circuit responsive to a read cycle to activate said first control signal while said second control signal is inactive, to activate said second control while said first control signal remains active, and to deactivate said first control signal while said second control signal remains active.

16. The memory of claim 15 wherein said local data line precharge circuit further has a control input for receiving a third control signal, and said control circuit activates said third control signal substantially while said first control signal is inactive.

17. The memory of claim 15 wherein said local data line precharge circuit further comprises:

a first transistor having a first current electrode for receiving said first voltage, a control electrode for receiving said third control signal, and a second current electrode coupled to a first local data line of said local data line pair;

a second transistor having a first current electrode for receiving said first voltage, a control electrode for receiving said third control signal, and a second current electrode coupled to a second local data line of said local data line pair; and

a third transistor having a first current electrode coupled to said first local data line of said local data line pair, a control electrode for receiving said third control signal, and a second current electrode coupled to said second local data line of said local data line pair.

18. The memory of claim 15 wherein said global data line precharge circuit further has a control input for receiving a fourth control signal, and said control circuit activates said fourth control signal substantially while said second control signal is inactive.

19. The memory of claim 16 wherein said global data line precharge circuit comprises:

a fourth transistor having a first current electrode coupled to a first global data line of said global data line pair, a control electrode for receiving said fourth control signal, and a second current electrode for receiving said second voltage;

a fifth transistor having a first current electrode coupled to a second global data line of said global data line pair, a control electrode for receiving said fourth control signal, and a second current electrode for receiving said second voltage; and

a sixth transistor having a first current electrode coupled to said first global data line of said global data line pair, a control electrode for receiving said fourth control signal, and a second current electrode coupled to said second global data line of said global data line pair.

20. The memory of claim 15 wherein:

said local sense amplifier comprises a programmable delay element having a first input for receiving said first control signal, and a second input for receiving a first fuse signal; and

said global sense amplifier comprises a second programmable delay element having a first input for receiving said second control signal, and a second input for receiving a second fuse signal.