Method and system for low power refresh of dynamic random access memories
First Claim
1. A method of operating a DRAM device in either a high power, full density mode or a low power, half density low mode, comprising:
- reordering each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address;
when operating in the full density mode, accessing rows of memory cells in an array according to the reordered row address;
when operating in the full density mode, refreshing the memory cells in the array at a first rate;
when operating in the half density mode, accessing rows of memory cells in the array according to the reordered row address, and, when accessing each row of memory cells, also accessing an adjacent row of memory cells;
when operating in the half density mode, refreshing memory cells in the memory array at a second rate that is slower than the first rate; and
when switching from operation in the full density mode to operation in the half density mode, transferring data from each row of the array in which data are stored to the adjacent row of memory cells.
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Abstract
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.
76 Citations
48 Claims
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1. A method of operating a DRAM device in either a high power, full density mode or a low power, half density low mode, comprising:
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reordering each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address;
when operating in the full density mode, accessing rows of memory cells in an array according to the reordered row address;
when operating in the full density mode, refreshing the memory cells in the array at a first rate;
when operating in the half density mode, accessing rows of memory cells in the array according to the reordered row address, and, when accessing each row of memory cells, also accessing an adjacent row of memory cells;
when operating in the half density mode, refreshing memory cells in the memory array at a second rate that is slower than the first rate; and
when switching from operation in the full density mode to operation in the half density mode, transferring data from each row of the array in which data are stored to the adjacent row of memory cells. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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2-39. -39. (canceled)
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46. A method of operating a DRAM device, comprising:
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reordering row addresses applied to the DRAM device by offsetting row addresses with respective row address offsets so that addresses having sequential row address values correspond to respective rows of memory cells in the DRAM device that are spaced apart from each other by a predetermined number of rows; and
accessing rows of memory cells in a memory array according to the reordered row address. - View Dependent Claims (47, 48)
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Specification