Method and system for low power refresh of dynamic random access memories
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Abstract
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.
87 Citations
46 Claims
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1-39. -39. (canceled)
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40. A method of operating a DRAM device in either a first relatively higher power mode or a second, relatively higher power mode, comprising:
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when operating in the first mode, refreshing rows of memory cells in an array one-row-at-a-time at a first rate;
when operating in the second mode, refreshing rows of memory cells in the array multiple rows-at-a-time at a second rate that is slower than the first rate; and
when switching from operation in the first mode to operation in the second mode, transferring data from each row of the array in which data are stored to at least one other row of memory cells. - View Dependent Claims (41, 42, 43, 44, 45, 46)
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Specification