Self-aligned trench MOSFET structure and method of manufacture

• US 20070173021A1
• Filed: 01/25/2006
• Published: 07/26/2007
• Est. Priority Date: 01/25/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kraft, Nathan, Kocon, Christopher
• Granted Patent: US 7,452,777 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

Claims

1. A method of forming a trench gate field effect transistor (FET) in a semiconductor die comprising an active region for housing active transistor cells and a termination region surrounding the active region, the method comprising:

forming a well region in the active region and the termination region at the same time, the well region being formed in a silicon region having a conductivity type opposite that of the well region;

simultaneously forming a plurality of active gate trenches in the active region and a non-active termination trench in the termination region, the plurality of active gate trenches and the non-active termination trench extending into and penetrating through the well region to there by divide the well region into a plurality of active body regions in the active region and a termination body region in the termination region;

using a mask, forming an opening over the termination body region and an opening over the active region;

implanting dopants into the active body regions through the opening over the active region and into the termination body region through the opening over the termination body region, thereby forming a first region in each active body region and in the termination body region, the first regions having a conductivity type opposite that of the well region; and

recessing exposed surfaces of all first regions using a silicon etch to form a bowl-shaped silicon recess having slanted walls and a bottom protruding through each first region such that portions of each first region remain in a corresponding active body region, the remaining portions of the first regions in the active body regions forming source regions which are self-aligned to the active gate trenches.

2. The method of claim 1 further comprising:

implanting dopants into the bowl-shaped silicon recesses to form a heavy body region in each active body region and in the termination body region, the heavy body regions having the same conductivity type as the well region.

3. The method of claim 2 further comprising:

forming a metal layer over the semiconductor die;

patterning the metal layer to form;

(i) a source metal layer extending into each bowl-shaped silicon recess in the active region to electrically contact the source regions and the heavy body regions in the active region, and (ii) a field plate extending into the non-active termination trench and into the bowl-shaped silicon recess formed in the termination body region to electrically contact the heavy body region formed in the termination body region, wherein the source metal layer and the field plate are insulated from one another.

4. The method of claim 1 further comprising:

forming a termination dielectric layer in the non-active termination trench;

forming a field plate comprising conductive material in the trench over the termination dielectric layer, the termination dielectric layer insulating all portions of the field plate inside the non-active termination trench from all silicon regions surrounding the non-active termination trench, the field plate extending out of the non-active termination trench and into the bowl-shaped silicon recess formed in the termination body region to thereby electrically contact the heavy body region formed in the termination body region.

5. The method of claim 4 wherein the conductive material is a metal.

6. The method of claim 1 further comprising:

forming a gate dielectric layer lining sidewalls of each active gate trench;

forming a recessed gate in each active gate trench, wherein the termination dielectric layer is thicker than the gate dielectric layer; and

forming a dielectric material over each recessed gate.

7. The method of claim 1 wherein the non-active termination trench extends to an edge of the semiconductor die such that the non-active termination trench forms a vertical wall at which the well region terminates.

8. The method of claim 1 wherein the active gate trenches and the non-active termination trench terminate at the same depth.

9. The method of claim 1 wherein the termination body region is electrically unbiased so that it floats during operation.

10. The method of claim 1 wherein the simultaneously forming step comprises:

forming non-active gate runner trenches at the same time the active gate trenches and the non-active termination trench are formed, the non-active gate runner trench, the active gate trenches and the non-active termination trench extending to the same depth; and

forming a recessed gate electrode in each active gate trench and a recessed gate runner electrode in the non-active gate runner trench at the same time, the recessed gate electrode in each active gate trench being electrically connected to the recessed gate runner electrode in the non-active gate runner trench.

11. The method of claim 10 wherein the non-active gate runner trench is wider than the active gate trenches.

12. The method of claim 10 wherein the active gate trenches are stripe shaped extending along a first direction, and the non-active gate runner trench extends, at least in part, along a direction perpendicular to and is contiguous with the active gate trenches.

13. A method of forming a trench gate field effect transistor (FET) in a semiconductor die comprising an active region wherein active transistor cells are formed and a termination region surrounding the active region, the method comprising:

forming a well region in the active region and the termination region at the same time, the well region being formed in a silicon region having a conductivity type opposite that of the well region;

simultaneously forming a plurality of active gate trenches in the active region, a non-active gate runner trench, and a non-active termination trench in the termination region, the plurality of active gate trenches, the non-active gate runner trench, and the non-active termination trench extending into and penetrating through the well region to thereby divide the well region into a plurality of active body regions in the active region and a termination body region in the termination region;

forming a recessed active gate electrode in each active gate trench and a recessed gate runner electrode in the non-active gate runner trench at the same time, the recessed active gate electrodes being electrically connected to the recessed gate runner electrode;

defining an opening over the termination body region and an opening over the active region using a mask;

implanting dopants into the active body regions through the opening in the active region and into the termination body region through the opening over the termination body region, thereby forming a first region in each active body region and in the termination body region, the first regions having a conductivity type opposite that of the well region; and

recessing exposed surfaces of all first regions using a silicon etch to form a bowl-shaped silicon recess having slanted walls and a bottom protruding through the first region such that portions of each first region remain in a corresponding active body region, the remaining portions of the first region in the active body regions forming source regions which are self-aligned to the active gate trenches.

14. The method of claim 13 further comprising:

implanting dopants into the bowl-shaped silicon recesses to form a heavy body region in each active body region and in the termination body region, the heavy body regions having the same conductivity type as the well region.

15. The method of claim 13 further comprising:

forming a termination dielectric layer in the non-active termination trench;

forming a field plate comprising conductive material in the non-active termination trench, the termination dielectric layer insulating all portions of the field plate inside the non-active termination trench from all silicon regions surrounding the non-active trench termination, the field plate extending out of the non-active termination trench and into the bowl-shaped silicon recess formed in the termination body region to thereby electrically contact the heavy body region formed in the termination body region.

16. The method of claim 15 wherein the conductive material is a metal.

17. The method of claim 15 further comprising:

prior to forming the recessed active gate electrode and the recessed gate runner electrode, forming a gate dielectric layer lining sidewalls of each active gate trench.

18. The method of claim 15 wherein the non-active termination trench extends to an edge of the die such that the non-active termination trench forms a vertical wall at which the well region terminates.

19. The method of claim 13 wherein the active gate trenches, the non-active gate runner trench, and the non-active termination trench terminate at the same depth.

20. The method of claim 13 wherein the termination body region is electrically unbiased so that it floats during operation.

21. The method of claim 13 wherein the non-active gate runner trench is wider than the active gate trenches.

22. The method of claim 13 wherein the active gate trenches are stripe shaped extending along a first direction, and the non-active gate runner trench extends, at least in part, along a direction perpendicular to and is contiguous with the active gate trenches.