Early conditional selection of an operand

• US 20070174592A1
• Filed: 01/20/2006
• Published: 07/26/2007
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sartorius, Thomas, Dieffenderfer, James, Bridges, Jeffrey, McIlvaine, Michael
• Granted Patent: US 9,710,269 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

Claims

1. A method of pipeline operation, comprising:

detecting an instruction that specifies at least one operand to be selected from a group of at least two operands at least one of which may be in flight in the pipeline;

determining an operand selection criterion as specified by the instruction;

evaluating the operand selection criterion to select at least one operand from the group of at least two operands; and

committing the instruction for execution once the at least one selected operand is available without waiting for a non-selected operand to become available.

2. The method of claim 1 wherein the determining a selection criterion further comprises:

decoding the instruction to determine at least one condition flag that is used as the basis for the selection criterion.

3. The method of claim 1 wherein the evaluating the selection criterion further comprises:

waiting for condition flags that are specified by the selection criterion to be affected if the condition flags may be affected by a previous instruction still in execution.

4. The method of claim 2 wherein the step to determine at least one condition flag further comprises:

looking ahead in the processor execution pipeline stages to check if the at least one condition flag may be affected by a previous instruction in execution.

5. The method of claim 1 wherein at least two operands are to be selected and wherein the group comprises at least three operands.

6. The method of claim 1 wherein the instruction specifies a function of the at least one selected operand.

7. The method of claim 6 wherein the function returns a calculated result based on the at least one selected operand.

8. The method of claim 1 wherein a block of at least two operands are to be selected from a group of blocks of operands wherein each block of operands has two or more operands.

9. The method of claim 1 wherein the selection criterion is based on at least one packed data byte condition indication.

10. A method of processing a select operand instruction in a processor pipeline, the method comprising:

decoding a selection criteria specified in the select operand instruction in a decode stage of the processor pipeline;

analyzing condition flags specified by the selection criteria; and

if the analysis of the condition flags indicates that at least one operand of a group of at least two operands specified in the select operand instruction is to be selected, terminating any wait that may be in effect for a non-selected operand; and

executing the select operand instruction with the at least one selected operand.

11. The method of claim 10 wherein the analyzing condition flags further comprises:

waiting for the condition flags specified by the selection criteria to be affected if the condition flags may be affected by a previous instruction still in execution.

12. The method of claim 10 wherein the group of at least two operands comprises a register operand and an immediate value operand.

13. The method of claim 10 wherein the executing the select operand instruction further comprises:

returning a result that is a function of the at least one selected operand.

14. A pipelined processor for processing instructions, the pipelined processor comprising:

an execution stage for executing instructions using input operand data required by each instruction of a plurality of instructions;

a hold circuit for generating a hold for each of the plurality of instructions in turn, prior to execution thereof by the execution stage, until completion of receiving the input operand data for each instruction; and

means for determining, prior to completion of receiving the input operand data, an operand data to select and terminating the hold with respect to a selection criteria specified in an instruction in execution upon determining the selected operand data is available.

15. The pipelined processor of claim 14 wherein terminating the hold further comprises terminating a fetch operation for input operand data not necessary for an instruction to complete execution.

16. The pipelined processor of claim 14 further comprises:

a decoder for decoding each instruction of the plurality of instructions into control bits including control bits that specify condition codes which represent the selection criteria; and

pipeline stages that track the control bits stage by stage through the pipeline.

17. The pipelined processor of claim 16 wherein the control bits are readable in each pipeline stage to determine if an execution stage may affect the condition codes.

18. The pipelined processor of claim 14 wherein the instruction in execution comprises at least one bit field that specifies a select operand instruction and specifies a selection criteria for selecting at least one operand from a group of at least two operands and at least one bit field for each operand that is to be selected from.

19. The pipelined processor of claim 18 wherein the instruction further comprises a bit field that specifies a function of the selected at least one operand.

20. The pipelined processor of claim 18 wherein the at least one bit field for each operand is an address pointing to a block of operand data elements.