Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
First Claim
1. A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:
- receiving a physical layout of the die;
partitioning the die into an array of tiles;
computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die;
applying a random variation for the quality indicative parameter to each tile in the array of tiles; and
obtaining the manufacturing yield for the die based on both the systematic variations and the random variations.
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Abstract
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
43 Citations
27 Claims
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1. A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:
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receiving a physical layout of the die;
partitioning the die into an array of tiles;
computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die;
applying a random variation for the quality indicative parameter to each tile in the array of tiles; and
obtaining the manufacturing yield for the die based on both the systematic variations and the random variations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:
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receiving a physical layout of the die;
partitioning the die into an array of tiles;
computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die;
applying a random variation for the quality indicative parameter to each tile in the array of tiles; and
obtaining the manufacturing yield for the die based on both the systematic variations and the random variations. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus for predicting a manufacturing yield for a die within a semiconductor wafer, the apparatus comprising:
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a receiving mechanism configured to receive a physical layout of the die;
a partitioning mechanism configured to partition the die into an array of tiles;
a computing mechanism configured to compute systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die;
an applying mechanism configured to apply a random variation for the quality indicative parameter to each tile in the array of tiles; and
an obtaining mechanism configured to obtain the manufacturing yield for the die based on both the systematic variations and the random variations. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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Specification