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Predicting IC manufacturing yield by considering both systematic and random intra-die process variations

  • US 20070174797A1
  • Filed: 01/24/2006
  • Published: 07/26/2007
  • Est. Priority Date: 01/24/2006
  • Status: Active Grant
First Claim
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1. A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:

  • receiving a physical layout of the die;

    partitioning the die into an array of tiles;

    computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die;

    applying a random variation for the quality indicative parameter to each tile in the array of tiles; and

    obtaining the manufacturing yield for the die based on both the systematic variations and the random variations.

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