Firmware socket module for FPGA-based pipeline processing

• US 20070174841A1
• Filed: 01/26/2006
• Published: 07/26/2007
• Est. Priority Date: 01/26/2006
• Status: Active Grant

• Current Assignee: Ip Reservoir, LLC
• Original Assignee: Exegy Incorporated & Washington University
• Inventors: Henrichs, Michael, Brodie, Benjamin, White, Jason, Chamberlain, Roger, Shands, E. F.
• Granted Patent: US 7,954,114 B2
• Time in Patent Office: Days
• US Class Current: 719/310
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module has a communication path between itself and an entry point into a data processing pipeline, wherein the firmware socket module is configured to provide both commands and target data to the entry point in the data processing pipeline via the same communication path, wherein each command defines a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation. Preferably, the firmware socket module is configured to provide the commands and target data in a predetermined order that is maintained throughout the data processing pipeline. Also, the firmware socket module may be configured to (1) access an external input descriptor pool buffer that defines the order in which commands and target data are to be provided to the data processing pipeline, and (2) transfer the commands and target data from an external memory to the data processing pipeline in accordance with the identified defined order. Results of the processing by the data processing pipeline are also returned to external memory by the firmware socket module, whereupon those results can be subsequently used by software executing on a computer system.

Claims

1. A method of interfacing at least one firmware application module that is deployed on a reconfigurable logic device with a computer system, the computer system comprising a processor and a memory space that are in communication with each other, wherein the at least one firmware application module is configured to perform a data processing operation on any target data that it receives, the method comprising:

within a firmware module that is deployed on the reconfigurable logic device and that interfaces the at least one firmware application module to the computer system memory space, (1) reading from a buffer within the memory space to identify a plurality of commands and target data that are to be provided to the at least one firmware application module, wherein the buffer defines an order in which the commands and target data are to be provided to the at least one firmware application module, each command controlling the data processing operation that the at least one firmware application module is to perform on any target data that it receives, and (2) transferring commands and target data from the computer system memory to the at least one firmware application module in accordance with the defined order.

2. The method of claim 1 further comprising:

processing the transferred commands and target data through the at least one firmware application module as a stream of interleaved commands and target data.

3. The method of claim 2 wherein a communication path links the firmware module with the at least one firmware application module, and wherein the transferring step comprises providing the commands and target data to the at least one firmware application module over the same communication path.

4. The method of claim 3 wherein the at least one firmware application module comprises a plurality of firmware application modules that are arranged in a pipeline, the pipeline having a first firmware application module and a final firmware application module, wherein the transferring step further comprises transferring, over the same communication path, the commands and target data from the computer system memory to the first firmware application module of the pipeline in accordance with the determined order.

5. The method of claim 4 wherein the processing step further comprises sequentially processing the transferred commands and target data through each additional firmware application module of the pipeline culminating in the final firmware application module of the pipeline.

6. The method of claim 5 wherein a plurality of the commands are specific to individual ones of the firmware application modules.

7. The method of claim 6 wherein at least one of the commands comprises a pass through command to one of the firmware application modules.

8. The method of claim 6 wherein the data processing operations defined by the commands comprise at least two members of the group consisting of a search operation, a data reduction operation, an encryption operation, a decryption operation, a compression operation, a decompression operation, and a pass through operation.

9. The method of claim 5 wherein the computer system memory space includes random access memory (RAM), and wherein the external buffer is stored in the RAM.

10. The method of claim 9 further comprising:

managing the external buffer with a device driver that operates under control of the processor.

11. The method of claim 10 wherein the buffer comprises a first buffer, wherein the final firmware application module of the pipeline is configured to produce an output as a result of the data processing operation that it performs on any target data that it receives, the method further comprising:

via an additional communication path that links the final firmware application module with the firmware module, transferring the final firmware application module'"'"'s output to the firmware module; and

within the firmware module, (1) reading an additional buffer managed by the device driver to determine a location in the computer system memory space where the final firmware application module'"'"'s output is to be stored, and (2) transferring the final firmware application module'"'"'s output to the determined location in the computer system memory.

12. The method of claim 10 further comprising:

storing the target data in the computer system memory space in contiguous memory addresses in the same order as the target data are to be provided to the firmware application module pipeline.

13. The method of claim 12 wherein the managing step comprises populating the first buffer with pointers to the memory space addresses where the commands and target data are stored in the computer system memory space.

14. The method of claim 13 wherein the populating step comprises storing the pointers in the first buffer in the same order as the commands and target data corresponding thereto are to be provided to the firmware application module pipeline.

15. The method of claim 4 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

16. A method for controlling the flow of data and commands to at least one firmware application module that is deployed on a re-configurable logic device, the commands comprising instructions for controlling the processing of the data by the at least one firmware application module, the method comprising:

providing a common communication path to said at least one firmware application module; and

delivering both the commands and data over the common communication path to said at least one firmware application module.

17. The method of claim 16 wherein the at least one firmware application module comprises a plurality of firmware application modules arranged in a pipeline, and wherein the delivering step comprises delivering a stream of interleaved commands and data to a first one of the firmware application modules in the pipeline.

18. The method of claim 17 wherein at least a plurality of the commands are specific to individual ones of the firmware application modules in the pipeline.

19. A data processing device comprising:

a firmware socket module in communication with a data processing pipeline, said data processing pipeline being deployed on at least one reconfigurable logic device, and wherein the firmware socket module is configured to control the propagation of both commands and target data to the data processing pipeline via a communication path common to both the commands and the target data, wherein each command controls a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation.

20. The data processing device of claim 19 wherein the firmware socket module is also deployed on the at least one reconfigurable logic device.

21. The data processing device of claim 20 wherein the data processing pipeline comprises a plurality of firmware application modules that are connected in series, wherein the firmware socket module is configured to provide the commands and target data in a predetermined order to an entry point into the data processing pipeline, and wherein the predetermined order is maintained throughout the data processing pipeline.

22. The data processing device of claim 21 wherein the firmware socket module is configured to (1) access an external input descriptor pool buffer to identify where in an external memory space the commands and target data to be delivered to the data processing pipeline are stored, wherein the input descriptor pool buffer defines the order in which commands and target data are to be delivered to the data processing pipeline, and (2) transfer the identified commands and target data from the external memory space to the data processing pipeline in accordance with the defined order.

23. The data processing device of claim 22 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), wherein the firmware socket module has another communication path between itself and an exit point from the data processing pipeline, wherein the firmware socket module is further configured to receive an output from the data processing pipeline via the additional communication path.

24. The data processing device of claim 23 wherein the firmware socket module is further configured to (1) access a first external output descriptor pool buffer to identify a location in the memory space where command output from the data processing pipeline should be stored, (2) access a second external output descriptor pool buffer to identify a location in the memory space where target data output from the data processing pipeline should be stored, and (3) write the command output and the target data output from the data processing pipeline to their respective identified locations in the memory space.

25. A data processing system comprising:

a processor;

a memory space that is managed by the processor;

a reconfigurable logic device, the reconfigurable logic device comprising at least one firmware application module that is deployed thereon and a firmware socket module that interfaces the at least one firmware application module with the processor and the memory, the firmware socket module and the at least one firmware application module being in communication with each other via a communication path; and

a bus through which the reconfigurable logic device communicates with the processor and the memory space; and

wherein the firmware application module is configured to perform a data processing operation on a data stream that it receives;

wherein the firmware socket module is configured to receive both a plurality of commands and target data from the memory space;

wherein the firmware socket module is configured provide both the commands and the target data to the at least one firmware application module via the same communication path between itself and the at least one firmware application module, wherein each command controls the data processing operation that is performed by the at least one firmware application module, and wherein the target data comprises the data upon which the at least one firmware application module'"'"'s data processing operation is performed.

26. The system of claim 25 wherein the firmware socket module is further configured to (1) receive the commands and the target data as a stream of interleaved and ordered commands and target data, and (2) maintain the order or the ordered commands and target data when it provides the stream to the at least one firmware application module via the same communication path.

27. The system of claim 26 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

28. The system of claim 27 wherein the at least one firmware application module comprises a plurality of firmware application modules that are arranged in a pipeline, wherein each of the firmware application modules in the pipeline are configured to sequentially process the commands and the target data of the stream in the same order in which the firmware socket module provided the commands and the target data.

29. The system of claim 28 wherein a plurality of the commands are specific to individual ones of the firmware application modules in the pipeline.

30. The system of claim 28 wherein the firmware application modules and the firmware socket module are arranged in a chain, wherein the firmware socket module provides the stream of interleaved and ordered commands and target data to the first one of the firmware application modules in the pipeline.

31. The system of claim 28 wherein the processor is further configured with a device driver that maintains a buffer in which data corresponding to a plurality of commands and data corresponding to a plurality of data streams are stored in said order, and wherein the firmware socket module is configured to access the buffer to identify the commands and the data streams to be processed through the firmware application modules.

32. The system of claim 31 wherein the commands and the target data are stored in the memory space at a plurality of memory addresses, and wherein the data corresponding to the plurality of commands and the data corresponding to the target data that are stored in the buffer comprise a plurality of pointers to the memory addresses where the corresponding commands and target data are stored.

33. The system of claim 32 wherein the target data that is to be processed as a group through the chain is stored in contiguous memory addresses in the same order as which pointers thereto are stored in the buffer.

34. The system of claim 27 wherein the data processing operations comprise at least two members of the group consisting of a search operation, an encryption operation, a decryption operation, a compression operation, a decompression operation, and a data reduction operation.

35. A data processing card for connection with a bus of a computer system, the data processing card comprising:

a reconfigurable logic device, the reconfigurable logic device having deployed thereon a firmware application module pipeline and a firmware module;

wherein the firmware module is configured to interface the firmware application module pipeline with at least one external source of target data and commands, wherein the commands control how the firmware application module pipeline processes target data;

wherein the firmware application module pipeline comprises a plurality of firmware application modules arranged in a sequence, each firmware application module being configured to perform a data processing operation on target data, the firmware application module pipeline having an entry communication path from the firmware module to a first one of the firmware application modules in the sequence;

wherein the firmware module is further configured to control how the firmware application module pipeline processes target data by providing, through the entry communication path, the first one of the firmware application modules in the sequence with a stream of interleaved commands and target data, wherein the commands and target data have a defined order within the stream;

wherein the firmware module is configured to read entries that are stored in an external buffer to determine the commands and the target data that are to be provided to the firmware application module pipeline, wherein the order of entries in the external buffer defines the order of commands and target data within the stream; and

wherein the firmware application module pipeline is configured to sequentially process the commands and target data of the stream through the sequence of firmware application modules in the same order in which those commands and target data were ordered within the stream.

36. The data processing card of claim 35 wherein the external buffer entries comprise pointers to addresses in the at least one external source where the commands and target data are stored, wherein the firmware module is further configured to access the at least one external source to retrieve, from the addresses, the commands and target data in accordance with the defined order.

37. The data processing card of claim 36 wherein a plurality of the commands are specific to individual ones of the firmware application modules in the sequence.

38. The data processing card of claim 37 wherein at least one of the commands comprises a pass through command to one of the firmware application modules in the sequence.

39. The data processing card of claim 37 wherein the data processing operations defined by the commands comprise at least two members of the group consisting of a search operation, a data reduction operation, an encryption operation, a decryption operation, a compression operation, a decompression operation, and a pass through operation.

40. The data processing card of claim 39 wherein the firmware application module pipeline further has an exit communication path from a final one of the firmware application modules in the sequence to the firmware module, wherein each data procession operation performed by the final one of the firmware application modules in the sequence produces an output, and wherein the firmware module is further configured to (1) receive the outputs from the final one of the firmware application modules in the sequence via the exit communication path, (2) read entries that are stored in an external buffer to determine a plurality of locations in the at least one external source where the outputs are to be stored, and (3) write the outputs to the at least one external source at the determined locations.

41. The data processing card of claim 35 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

42. A system controlling the processing of data through a reconfigurable logic device via software, the system comprising:

device driver software for execution by a processor, the device driver software being configured to manage a memory space in which data is stored at a plurality of memory addresses; and

a reconfigurable logic device for communicating with the device driver software and the memory space over a bus;

wherein at least one firmware application module and a firmware socket module are deployed on the reconfigurable logic device;

wherein the at least one firmware application module is configured to perform a data processing operation on any target data that it receives;

wherein the device driver software is configured to store a plurality of commands in the memory space, each command for controlling a data processing operation that is to be performed by the at least one firmware application module;

wherein the device driver software is further configured to maintain an input descriptor pool buffer in the memory space that defines an order in which commands and data are to be processed through the at least one firmware application module; and

wherein the firmware socket module is configured to (1) access the input descriptor pool buffer to identify the ordered commands and data that are to be processed through the at least one firmware application module, and (2) access the memory space to transfer the commands and data to the at least one firmware application module in accordance with the defined order.

43. The system of claim 42 wherein the at least one firmware application module comprises a plurality of firmware application modules that are arranged in a pipelined sequence, the pipelined sequence including a first firmware application module, wherein the firmware socket module is in communication with the first firmware application module of the pipelined sequence via a communication path, wherein the firmware socket module is further configured to transfer the commands and data to the first firmware application module in the pipelined sequence over the same communication path.

44. The system of claim 43 wherein each command includes a firmware application module identifier that identifies the firmware application module in the pipelined sequence to which that command is applicable.

45. The system of claim 44 wherein the device driver software is further configured to maintain the input descriptor pool buffer by storing therein a plurality of pointers to memory addresses in the memory space where the commands and data to be processed through the pipelined sequence of firmware application modules are stored, wherein the order of pointers in the input descriptor pool buffer defines the order in which commands and data are provided to the pipelined sequence of firmware application modules by the firmware socket module.

46. The system of claim 45 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), the system further comprising application software for execution by the processor and module application programming interface software for execution by the processor, wherein the application software is configured to receive input from a user that specifies (1) at least one data processing operation to be performed by the pipelined sequence of firmware application modules and (2) the data upon which the pipelined sequence of firmware application modules will perform the at least specified data processing operation, and wherein module application programming interface software is configured to interface the application software with the device driver software such that the device driver software appropriately manages the input descriptor pool buffer and the memory space in accordance with the user input.

47. The system of claim 45 wherein the device driver software is further configured to store the data to be processed through the pipelined sequence in contiguous memory addresses of the memory space in same order as that data is to be provided to the pipelined sequence of firmware application modules.

48. A device for interfacing a pipeline of firmware application modules that are deployed on at least one reconfigurable logic device with a memory space that is external to the reconfigurable logic device, the device comprising:

a firmware module that is deployed the at least one reconfigurable logic device, wherein the firmware module is configured to (1) serially access the external memory space to retrieve a plurality of commands and a plurality of groups of target data in an order and (2) deliver both the retrieved commands and target data groups to an entry point in the pipeline as a single interleaved stream in the same order over a common communication path that connects the firmware module with the entry point into the pipeline, wherein each firmware application module in the pipeline is configured to perform a data processing operation on any target data that it receives, and wherein each command is configured to control the data processing operation of at least one firmware application module in the pipeline.

49. The device of claim 48 wherein the firmware module is further configured determine which commands and which target data groups are to be retrieved from the external memory space by reading an ordered set of descriptors that are stored in the external memory space by a software program executed by an external processor, wherein the ordered set of descriptors defines the order in which commands and target data groups are to be interleaved in the stream.