Varying mesa dimensions in high cell density trench MOSFET

• US 20070176231A1
• Filed: 07/07/2006
• Published: 08/02/2007
• Est. Priority Date: 01/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Wang, Qi, Sim, Gordon
• Granted Patent: US 7,667,265 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Circuits, methods, and apparatus for power MOSFETs having a high cell density for a high current carrying capability while maintaining a low pinched-base resistance. One device employs a number of transistor cells having varying mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage. The large cell BVDSS can be varied by adjusting the critical dimension or width of the trench gates on either side of the wider mesas, or by adjusting the depth of the heavy body etch.

Claims

1. A trench-gate power MOSFET device comprising:

a first plurality of cells having a first cell pitch, the first plurality of cells formed using a heavy body etch;

a second plurality of cells having a second cell pitch, the second cell pitch narrower than the first cell pitch, the second plurality of cells formed not using the heavy body etch.

2. The device of claim 1 wherein the heavy body etch is used to control a body-diode breakdown voltage for the first plurality of cells.

3. The device of claim 1 wherein a width of a trench is used to control a body-diode breakdown voltage for the first plurality of cells.

4. The device of claim 1 wherein a desired turn off current specification is used to determine a number of cells in the first plurality of cells.

5. The device of claim 4 wherein a desired on resistance is used to determine a number of cells in the second plurality of cells.

6. The device of claim 1 wherein the second pitch is determined by minimum design rules.

7. A trench-gate power MOSFET device comprising:

a first trench gate;

a second trench gate displaced from the first trench gate by a first distance;

a third trench gate displaced from the second trench gate by a second distance;

a first body region comprising a first well and located between the first trench gate and the second trench gate; and

a second body region comprising a second well and located between the second trench gate and the third trench gate;

wherein the first body region is processed to have a lower pinched-base resistance and a lower drain-to-bulk breakdown voltage than the second body region, and

wherein the first distance is larger than the second distance.

8. The device of claim 7 wherein the first body region is processed using a heavy body etch.

9. A method of manufacturing a trench-gate power MOSFET device comprising:

using a drain-to-bulk breakdown specification to determine a width of a wide cell;

using the drain-to-bulk breakdown specification to determine a first width of a trench-gate for a wide cell;

using a avalanche current specification to determine a first number of wide cells;

using design rule limitations to determine a width of a narrow cell; and

using an on resistance specification to determine a second number of narrow cells.

10. The method of claim 9 further comprising:

laying out a device having;

the first number of wide cells; and

the second number of narrow cells,

wherein the wide cells are bounded by trench gates having the first width.

11. A method of designing a trench-gate power MOSFET comprising:

determining a first physical parameter for a first cell type such that a first electrical characteristic for the first cell type meets a first requirement;

determining a second physical parameter for a second cell type such that the first electrical characteristic for the second cell type exceeds the first electrical characteristic for the first cell type;

determining a first number of the first cell type that are needed to meet a second requirement; and

determining a second number of the second cell type that are needed to meet a third requirement.

12. The method of claim 11 wherein the first physical parameter is a cell width.

13. The method of claim 11 wherein the first physical parameter is a depth of a heavy body etch.

14. The method of claim 11 wherein the first physical parameter is a trench width.

15. The method of claim 11 wherein the first electrical characteristic is a body-diode breakdown voltage.

16. The method of claim 11 wherein the second physical parameter is cell width.

17. The method of claim 16 wherein the width is determined by minimum design rules.

18. The method of claim 11 wherein the second requirement is a desired turn off current specification.

19. The method of claim 11 wherein the third requirement is an on resistance specification.

20. The method of claim 11 further comprising:

laying out a device having the first number of the first cell type and the second number of the second cell type.