DRAM access transistor and method of formation

• US 20070176232A1
• Filed: 04/03/2007
• Published: 08/02/2007
• Est. Priority Date: 09/17/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Luan C. Tran
• Inventors: Tran, Luan
• Granted Patent: US 7,547,604 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Claims

1-99. -99. (canceled)

100. A method of forming a recessed gate structure, comprising the acts of:

forming insulating columns directly on a top surface of a semiconductor substrate;

forming at least a trench within said semiconductor substrate and adjacent said insulating columns, wherein a width of said trench is less than a distance by which said insulating columns are spaced apart;

forming a gate oxide on the bottom and sidewalls of said trench; and

forming a conductive region at least partially within said trench.

101. The method of claim 100, wherein said distance by which said insulating columns are spaced apart is about 50 nm to about 100 nm.

102. The method of claim 100, wherein said insulating columns are formed to a height of about 20 nm to about 800 nm.

103. The method of claim 100, wherein said trench is etched to a depth of about 200 nm to about 700 nm.

104. The method of claim 103, wherein said trench is formed to a width of less than about 75% of said distance by which said insulating layers are spaced apart.

105. The method of claim 100, wherein said conductive region comprises polysilicon.

106. The method of claim 100, wherein said conductive region comprises a metal.

107. The method of claim 100, wherein said conductive region comprises a silicide.

108. A method of forming a transistor structure, the method comprising the acts of:

providing at least one trench structure within a substrate;

forming a first conductive region at least partially within said trench structure;

forming a second conductive region above said first conductive region and electrically connected to said first conductive region; and

forming source and drain regions within said semiconductor substrate on respective sides of said first conductive region.

109. The method of claim 108 further comprising the step of providing insulating spacers on sidewalls of said first conductive region but not on sidewalls of said second conductive region.

110. The method of claim 108, wherein said trench structure has a depth of about 200 nm to about 700 nm.

111. The method of claim 108, wherein said first conductive region comprises polysilicon and said second conductive region comprises a metal.

112. The method of claim 108, wherein said second conductive region comprises a metal silicide.