DRAM access transistor and method of formation
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Abstract
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.
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Citations
112 Claims
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1-99. -99. (canceled)
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100. A method of forming a recessed gate structure, comprising the acts of:
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forming insulating columns directly on a top surface of a semiconductor substrate;
forming at least a trench within said semiconductor substrate and adjacent said insulating columns, wherein a width of said trench is less than a distance by which said insulating columns are spaced apart;
forming a gate oxide on the bottom and sidewalls of said trench; and
forming a conductive region at least partially within said trench. - View Dependent Claims (101, 102, 103, 104, 105, 106, 107)
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108. A method of forming a transistor structure, the method comprising the acts of:
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providing at least one trench structure within a substrate;
forming a first conductive region at least partially within said trench structure;
forming a second conductive region above said first conductive region and electrically connected to said first conductive region; and
forming source and drain regions within said semiconductor substrate on respective sides of said first conductive region. - View Dependent Claims (109, 110, 111, 112)
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Specification