Semiconductor integrated circuit

• US 20070176233A1
• Filed: 12/15/2006
• Published: 08/02/2007
• Est. Priority Date: 01/27/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yasu, Yoshihiko, Mori, Ryo, Kuraishi, Takashi, Sasaki, Toshio, Ozawa, Osamu
• Granted Patent: US 7,714,606 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said MOS transistors being provided over an insulating thin film of a substrate;

wherein the plurality of MOS transistors are provided in mixed form in such a manner that the bodies thereof are brought into floating, the voltages of the bodies are fixed and the voltages of the bodies are set variable.

2. A semiconductor integrated circuit comprising:

a plurality of circuits constituted of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said circuits being provided over an insulating thin film of a substrate; and

a memory circuit included as part of the plurality of circuits,

wherein the memory circuit has memory elements constituted of MOS transistors whose body voltages are fixed.

3. The semiconductor integrated circuit according to claim 2, further including:

a digital circuit as part of the plurality of circuits,

wherein the digital circuit has sequence circuits constituted of MOS transistors whose body voltages are fixed.

4. The semiconductor integrated circuit according to claim 3, wherein the digital circuit has combination circuits constituted of MOS transistors whose bodies are brought into floating, and the combination circuits are connected in series with the sequence circuits respectively.

5. The semiconductor integrated circuit according to claim 4, further including:

another digital circuit as part of the plurality of circuits,

wherein said another digital circuit has a logic circuit constituted of MOS transistors whose bodies are brought into floating.

21. The semiconductor integrated circuit according to claim 2, further including:

a digital circuit as part of the plurality of circuits,

wherein the digital circuit has sequence circuits constituted of MOS transistors whose body voltages are fixed.

22. The semiconductor integrated circuit according to claim 21, wherein the digital circuit has combination circuits constituted of MOS transistors whose bodies are brought into floating, and the combination circuits are connected in series with the sequence circuits.

23. The semiconductor integrated circuit according to claim 22, further including:

another digital circuit as part of the plurality of circuits,

wherein the digital circuit has a logic circuit constituted of MOS transistors whose bodies are brought into floating.

24. The semiconductor integrated circuit according to claim 23, further including:

a control circuit, a controlled circuit and an external interface circuit as parts of the plurality of circuits,

wherein the control circuit variably controls a body potential of a body of each MOS transistor that constitutes the controlled circuit according to an operation mode.

25. The semiconductor integrated circuit according to claim 24, further including:

a body bias circuit, as another part of the plurality of circuits, which variably controls body potentials of MOS transistors constituting a subsequent-stage circuit on the basis of an output of a pre-stage circuit at a serial signal transmission path in the controlled circuit.

26. The semiconductor integrated circuit according to claim 25,

wherein the controlled circuit has a power supply switch, and a gate oxide film of the MOS transistor constituting the power supply switch has the same thickness as a gate oxide film of each of the MOS transistors for external input/output, constituting the external interface circuit, and

wherein the control circuit controls on/off of the power supply switch according to the operation mode.

27. The semiconductor integrated circuit according to claim 26, wherein the body of the MOS transistor constituting the power supply switch is connected to a source thereof.

28. The semiconductor integrated circuit according to claim 27, wherein the bodies of the MOS transistors constituting the external interface circuit are connected to sources thereof at plural spots.

29. The semiconductor integrated circuit according to claim 28, wherein in a low leak mode at shutoff of the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a reverse bias voltage at which a threshold voltage thereof becomes greater than when equal to a source voltage thereof, and in a high-speed mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a forward bias voltage at which the threshold voltage becomes smaller than when equal to the source voltage thereof.

30. The semiconductor integrated circuit according to claim 29, wherein in a low-speed mode at the supply of power by the power supply switch, the control circuit sets the body of each MOS transistor constituting the controlled circuit to the reverse bias.

31. The semiconductor integrated circuit according to claim 30, wherein in a normal mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a source voltage thereof.

32. The semiconductor integrated circuit according to claim 31, wherein upon power-on of the semiconductor integrated circuit, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of the MOS transistor prior to or simultaneously with the application of operating power to each MOS transistor constituting the controlled circuit.

33. The semiconductor integrated circuit according to claim 32, wherein upon power-off of the semiconductor integrated circuit, the control circuit shuts off the application of the bias voltage for holding the parasitic diode in the off state, which is applied to the body of the MOS transistor simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

34. The semiconductor integrated circuit according to claim 33, wherein when power on a high-potential side or a low-potential side is shut down by the power supply switch, the control circuit biases the body of each MOS transistor connected to the power supply switch to a power supply lying on the side opposite to the power supply shutdown by the power supply switch, or brings the same into floating.

35. The semiconductor integrated circuit according to claim 34, wherein when the supply of power by the power supply switch is resumed, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of each MOS transistor connected to the power supply switch prior to or simultaneously with an on operation of the power supply switch.

36. The semiconductor integrated circuit according to claim 35, further including:

an analog circuit as part of the plurality of circuits,

wherein the analog circuit has a circuit which allows each MOS transistor whose body voltage is fixed, to operate in a saturated region.

6. A semiconductor integrated circuit comprising:

a plurality of circuits constituted of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said circuits being provided over an insulating thin film of a substrate, and

a control circuit, a controlled circuit and an external interface circuit as parts of the plurality of circuits,

wherein the control circuit variably controls a body potential of each MOS transistor constituting the controlled circuit according to an operation mode.

7. The semiconductor integrated circuit according to claim 6, further including:

a body bias circuit, as another part of the plurality of circuits, which variably controls body potentials of MOS transistors constituting a subsequent-stage circuit on the basis of an output of a pre-stage circuit at a serial signal transmission path in the controlled circuit.

8. The semiconductor integrated circuit according to claim 6,

wherein the controlled circuit has a power supply switch, and a gate oxide film of the MOS transistor constituting the power supply switch has the same thickness as a gate oxide film of each of the MOS transistors for external input/output, constituting the external interface circuit, and

wherein the control circuit controls on/off of the power supply switch according to the operation mode.

9. The semiconductor integrated circuit according to claim 8, wherein the body of the MOS transistor constituting the power supply switch is connected to a source thereof.

10. The semiconductor integrated circuit according to claim 9, wherein the bodies of the MOS transistors constituting the external interface circuit are connected to sources thereof at plural spots.

11. The semiconductor integrated circuit according to claim 8, wherein in a low leak mode at shutoff of the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a reverse bias voltage at which a threshold voltage thereof becomes greater than when equal to a source voltage thereof, and in a high-speed mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a forward bias voltage at which the threshold voltage becomes smaller than when equal to the source voltage thereof.

12. The semiconductor integrated circuit according to claim 11, wherein in a low-speed mode at the supply of power by the power supply switch, the control circuit sets the body of each MOS transistor constituting the controlled circuit to the reverse bias.

13. The semiconductor integrated circuit according to claim 12, wherein in a normal mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a source voltage thereof.

14. The semiconductor integrated circuit according to claim 6, wherein when power of the semiconductor integrated circuit is turned on, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of the MOS transistor prior to or simultaneously with the application of operating power to each MOS transistor constituting the controlled circuit.

15. The semiconductor integrated circuit according to claim 14, wherein when the power of the semiconductor integrated circuit is turned off, the control circuit shuts off the bias voltage applied to hold the parasitic diode in the off state to the body of the MOS transistor simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

16. The semiconductor integrated circuit according to claim 6, wherein when the power of the semiconductor integrated circuit is turned on, the control circuit connects the body of the MOS transistor to a power supply on the source side prior to or simultaneously with the application of the operating power to each MOS transistor constituting the controlled circuit.

17. The semiconductor integrated circuit according to claim 16, wherein when the power of the semiconductor integrated circuit is turned off, the control circuit shuts off the connection between the body of the MOS transistor and the power supply on the source side simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

18. The semiconductor integrated circuit according to claim 8, wherein when power on a high-potential side or a low-potential side is shut down by the power supply switch, the control circuit biases the body of each MOS transistor connected to the power supply switch to a power supply lying on the side opposite to a power supply shutdown by the power supply switch, or brings the same into floating.

19. The semiconductor integrated circuit according to claim 18, wherein when the supply of power by the power supply switch is resumed, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of each MOS transistor connected to the power supply switch prior to or simultaneously with an on operation of the power supply switch.

20. The semiconductor integrated circuit according to claim 19, wherein when the supply of the power by the power supply switch is shut off, the control circuit shuts off the application of the bias voltage applied to hold the parasitic diode in the off state to the body of each MOS transistor connected to the power supply switch after or simultaneously with an off operation of the power supply switch.