Semiconductor devices having different gate dielectrics and methods for manufacturing the same

• US 20070176242A1
• Filed: 03/21/2007
• Published: 08/02/2007
• Est. Priority Date: 11/12/2003
• Status: Active Grant

• Current Assignee: Ho-Kyu Kang, Hyung-Suk Jung, Jong Ho Lee, Seok-Joo Doh, Yun-Seok Kim
• Original Assignee: Ho-Kyu Kang, Hyung-Suk Jung, Jong Ho Lee, Seok-Joo Doh, Yun-Seok Kim
• Inventors: Lee, Jong-Ho, Jung, Hyung-Suk, Kang, Ho-Kyu, Kim, Yun-Seok, Doh, Seok-Joo
• Granted Patent: US 7,586,159 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Claims

1. A semiconductor device comprising:

a first transistor comprising a first substrate region, a first gate electrode, and a first gate dielectric located between the first substrate region and the first gate electrode; and

a second transistor comprising a second substrate region, a second gate electrode, and a second gate dielectric located between the second substrate region and the second gate electrode;

wherein the first gate dielectric comprises a first high-k layer having a dielectric constant of 8 or more, wherein the second gate dielectric comprises a second high-k layer having a dielectric constant of 8 or more, and wherein the second high-k layer has a different material composition than the first high-k layer.

2. The semiconductor device as claimed in claim 1, wherein the first transistor is an NMOS device and the second transistor is a PMOS device.

3. The semiconductor device as claimed in claim 2, wherein the first high-k layer is hafnium oxide.

4. The semiconductor device as claimed in claim 2, wherein the first gate dielectric further comprises a first interface layer located between the first substrate region and the first high-k layer.

5. The semiconductor device as claimed in claim 4, wherein the first interface layer comprises a material selected from the group consisting of silicon oxide, silicon oxynitride, and silicate.

6. The semiconductor device as claimed in claim 2, wherein the second high-k layer is aluminum oxide.

7. The semiconductor device as claimed in claim 6, wherein the second gate dielectric further comprises a second interface layer located between the second substrate region and the second high-k layer.

8. The semiconductor device as claimed in claim 7, wherein the second interface layer comprises a material selected from the group consisting of silicon oxide, silicon oxynitride and silicate.

9. The semiconductor device as claimed in claim 2, wherein the first gate dielectric comprises a third high-k layer having a dielectric constant of 8 or more.

10. The semiconductor device as claimed in claim 9, wherein the first high-k layer is a hafnium oxide layer, and wherein the second and third high-k layers are aluminum oxide layers.

11. The semiconductor device as claimed in claim 10, wherein the second and third high-k layers are coplanar.

12. The semiconductor device as claimed in claim 11, wherein the third high-k layer is located between the first substrate region and the first high-k layer.

13. The semiconductor device as claimed in claim 10, wherein the first and second high-k layers are coplanar.

14. The semiconductor device as claimed in claim 13, wherein the first high-k layer is located between the first substrate region and the third high-k layer.

15. The semiconductor device as claimed in claim 10, wherein an interface layer between the first high-k layer and the third high-k layer is an alloy of materials of the first high-k layer and the third high-k layer.

16. The semiconductor device as claimed in claim 15, wherein the alloy comprises hafnium, aluminum and oxygen.

17. The semiconductor device as claimed in claim 2, wherein the second gate dielectric comprises a third high-k layer having a dielectric constant of 8 or more.

18. The semiconductor device as claimed in claim 17, wherein the first and third high-k layers comprise hafnium and oxygen, and wherein the second high-k layer comprises aluminum and oxygen.

19. The semiconductor device as claimed in claim 18, wherein the first and third high-k layers comprise hafnium oxide layers, and wherein the second high-k layer comprises an aluminum oxide layer.

20. The semiconductor device as claimed in claim 18, wherein the first and third high-k layers are coplanar.

21. The semiconductor device as claimed in claim 20, wherein the third high-k layer is located between the second substrate region and the second high-k layer.

22. The semiconductor device as claimed in claim 1, wherein the gate electrodes of each of the first transistor and the second transistor each comprise at least one of a metal and a metal nitride.

23. The semiconductor device as claimed in claim 1, wherein the gate electrodes of each of the first transistor and the second transistor each comprise at least one of a metal, a metal nitride and polysilicon.

24. The semiconductor device as claimed in claim 21, wherein each of the first and second high-k layers comprises nitrogen.

25. The semiconductor device as claimed in claim 18, wherein the first and second high-k layers are coplanar.

26. The semiconductor device as claimed in claim 25, wherein the second high-k layer is located between the second substrate region and the third high-k layer.

27. The semiconductor device as claimed in claim 18, wherein an intermediate layer between the second high-k layer and the third high-k layer is an alloy of materials of the second high-k layer and the third high-k layer.

28. The semiconductor device as claimed in claim 27, wherein the alloy comprises hafnium, aluminum and oxygen.

29. The semiconductor device as claimed in claim 2, wherein a thickness of the first gate dielectric and the second gate dielectric is in a range of 1 to 60 Å

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