REDUCED EDDY CURRENT LOSS IN LC TANK CIRCUITS

• US 20070176704A1
• Filed: 04/09/2007
• Published: 08/02/2007
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: LC Tank LLC
• Inventors: Gabara, Thaddeus
• Granted Patent: US 7,429,899 B2
• Time in Patent Office: Days
• US Class Current: 331/167
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1221 the amplifier comprising multiple amplification stages connected in cascade
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03B 5/1841 the frequency-determining element being a strip line resonator H03B5/1805, H03B5/1817, H03B5/1864 and H03B5/1882 take precedence

Abstract

Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Claims

1. An apparatus formed in a planar technology comprising:

at least one metallic conductor;

an eddy current loss; and

at least one space that is devoid of metal;

wherein

each space partitions a portion of the metallic conductor into at least two parallel conductor paths causing the eddy current loss to decrease.

2. The apparatus of claim 1 wherein at least one space is shaped as a polygon.

3. The apparatus of claim 1 wherein the space is filled with a dielectric layer.

4. The apparatus of claim 1 wherein at least two of the parallel conductor paths are magnetically coupled to each other.

5. The apparatus of claim 1 wherein one or more metallic conductors are used to form an inductor.

6. The apparatus of claim 5 wherein the type of inductor is selected from the group consisting of planar, coil and helix.

7. The apparatus of claim 5 wherein the inductor is formed using multiple metallic conductors vertically stacked on one another.

8. The apparatus of claim 7 wherein at least one dielectric layer is used to form the space.

10. The method of claim 8 wherein the one space is shaped as a polygon.

11. The method of claim 8 wherein the space is filled with a dielectric layer.

12. The method of claim 8 wherein at least two of the parallel conductor paths are magnetically coupled to each other.

13. The method of claim 8 wherein at least one metallic conductor is used to form an inductor.

14. The method of claim 12 wherein the type of inductor is selected from the group consisting of planar, coil and helix.

15. The method of claim 12 wherein the inductor is formed using multiple metallic conductors vertically stacked on one another.

16. The method of claim 15 wherein at least one dielectric layer is used to form a space.

9. A method of decreasing an eddy current loss within an apparatus formed in a planar technology comprising the steps of:

forming a metallic conductor;

creating at least one space that is devoid of metal; and

positioning the first space to partition a portion of the metallic conductor into at least two parallel conductor paths;

thereby

decreasing the eddy current loss within the apparatus.

17. An apparatus comprising:

one or more metal layers;

a plurality of metallic connections;

an eddy current loss;

a plurality of metallic conductors formed in at least one of the metal layers where each metallic conductor has a corresponding first lead and a corresponding second lead;

the corresponding first leads of the metallic conductors are connected together using the first metallic connection; and

the corresponding second leads of the metallic conductors are connected together using the second metallic connection.

18. The apparatus of claim 17 wherein at least two of the metallic conductors are magnetically coupled to each other.

19. The apparatus of claim 17 wherein at least two of the metallic conductors are juxtaposed to each other.

20. The apparatus of claim 17 wherein the metallic connection is provided by at least one via.

21. The apparatus of claim 17 wherein at least one metallic conductor contains at least one cross-under.

22. The apparatus of claim 17 wherein the metallic conductors are shaped as polygons.

23. The apparatus of claim 17, further comprising:

a least one dielectric component;

whereby

the dielectric component is used to fill an isolation region between at least two of the metallic conductors.

24. The method of claim 17 wherein

the metallic layers are planar.

25. The apparatus of claim 17 wherein

each of the plurality of metallic conductors have a corresponding width.

26. The apparatus of claim 17 wherein the corresponding widths are not equal.

27. The apparatus of claim 17 wherein the corresponding widths are substantially equal.

28. The apparatus of claim 27 wherein

the eddy current loss is reduced when compared to a second eddy current loss of a single metallic conductor with a conductor with substantially equal to the summation of all corresponding widths.

29. The apparatus of claim 27 wherein

a self-inductance of the apparatus is substantially equal to the self-inductance of a single metallic conductor with a conductor width substantially equal to the summation of all corresponding widths.

30. A composite inductor comprising:

a MCM (Multi Chip Modules) formed using at least two substrates;

a first lead electrically connected to opposing substrates via a first solder bump;

at least one other lead electrically connected to the opposing substrates via an other solder bump;

two or more inductors each with a corresponding width;

each inductor is coupled between the first lead and other lead;

at least one of the two inductors is located in the opposing substrate; and

the two or more inductors form the composite inductor having a combined width equal to the summation of the corresponding widths;

wherein

an eddy current loss within the composite inductor is reduced since each of the corresponding widths are less than the combined width of the composite inductor.

31. The circuit of claim 30 wherein at least two of the inductors are magnetically coupled to each other.

32. The circuit of claim 30 wherein at least two of the inductors are juxtaposed to each other.

33. The circuit of claim 30 wherein the corresponding widths are substantially the same.

34. The circuit of claim 30 wherein the corresponding widths are different.

35. An oscillator with an eddy current loss comprising:

at least one capacitor;

one or more planar inductor with a corresponding width;

means for forming a tank circuit using the at least one planar inductor and the at least one capacitor;

means for connecting a regenerative circuit to the tank circuit;

at least one addition planar inductor placed in parallel to the first planar inductor;

the two or more planar inductors from a composite inductor;

the composite inductor has a combined width determined by summing all corresponding metallic widths;

wherein

an eddy current loss within the composite inductor is reduced since each of the corresponding widths are less than the combined width of the composite inductor.

36. The oscillator of claim 35 wherein at least two of the planar inductors are magnetically coupled to each other.

37. The circuit of claim 35 wherein the oscillator drives at least one external capacitive load.

38. The circuit of claim 35 wherein the regenerative circuit is comprised of devices selected from the group consisting of MOS transistors, CMOS transistors, and BJT transistors.