Method for manufacturing semiconductor device

• US 20070178645A1
• Filed: 07/26/2006
• Published: 08/02/2007
• Est. Priority Date: 07/27/2005
• Status: Abandoned Application

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Aizawa, Osamu
• Application Number:
  US11/493,009
• Publication Number:
  US 20070178645A1
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

The present invention provides a method for manufacturing semiconductor device. An element isolation structural portion is formed in a semiconductor substrate, an element isolation gate insulating film is deposited, a floating gate film is deposited, a spacer film is deposited, and an etching resistant mask pattern is formed on the spacer film. Then, isotropic etching using the etching resistant mask pattern as a mask is performed to remove the spacer film lying in an area broader than an area exposed from the etching resistant mask pattern, which extends from an end edge portion of the etching resistant mask pattern to a lower surface of the etching resistant mask pattern to thereby form a spacer film pattern. Further, anisotropic etching using the etching resistant mask pattern as a mask is performed to remove the floating gate film thereby forming, at an upper end portion, a floating gate having an upper end surface portion placed at an obtuse angle to an exposed end surface.

Claims

1. A method for manufacturing a semiconductor device, comprising:

defining a plurality of element forming areas, an element isolation structural portion forming area which separates the respective adjacent element forming areas from each other;

forming an element isolation structural portion in the element isolation structural portion forming area;

depositing a gate oxide film which covers the upper surface of the substrate and the element isolation structural portion;

depositing a floating gate film over the gate oxide film;

depositing a spacer film over the floating gate film;

forming an etching resistant mask pattern covering the floating gate film over the spacer film;

performing isotropic etching using the etching resistant mask pattern as a mask to remove the spacer film in an area wider than an area exposed from the etching resistant mask pattern, extending from an end edge portion of the etching resistant mask pattern to a side below the etching resistant mask pattern, thereby forming a spacer film pattern having an end edge exposed portion;

performing anisotropic etching using the etching resistant mask pattern as a mask to remove the floating gate film thereby to form a floating gate pattern, the floating gate pattern having an exposed end portion including an obtuse angle with an exposed end surface of the floating gate pattern;

removing the etching resistant mask pattern and the spacer film pattern;

forming a second gate oxide film which covers the floating gate pattern;

depositing a control gate film over the second gate oxide film; and

patterning the control gate film to form a control gate pattern.

2. The method according to claim 1, further including a second isotropic etching for making the area of an upper end surface of the exposed end portion of the floating gate pattern larger, after forming the floating gate pattern and before removing the etching resistant mask pattern.

3. The method according to claim 1, wherein distance between the end edge portion of the etching resistant mask pattern and the exposed end portion of the floating gate pattern is equal to or greater than 40 nm in performing isotropic etching.

5. The method according to claim 1, further including a performing an etching for making the area of an upper end surface of the exposed end portion of the floating gate pattern larger, after forming the floating gate pattern and before removing the etching resistant mask pattern.

6. The method according to claim 1, wherein distance between the end edge portion of the etching resistant mask pattern and the exposed end portion of the floating gate pattern is equal to or greater than 40 nm in performing isotropic etching.

4. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

defining a plurality of active regions, a field region which separates the respective adjacent active regions on a surface of the semiconductor substrate;

forming a field insulating film in the field regions;

depositing a first gate insulating film which covers the active region;

depositing a floating gate film over the first gate insulating film;

depositing a spacer film over the floating gate film;

forming an etching resistant mask pattern covering the floating gate film over the spacer film;

removing the spacer film in an area wider than an area exposed from the etching resistant mask pattern by using the etching resistant mask pattern as a mask;

removing the floating gate film to form a floating gate pattern by using the etching resistant mask pattern as a mask;

removing the etching resistant mask pattern and the spacer film pattern;

forming a second gate insulating film which covers the floating gate pattern;

depositing a control gate film over the second gate insulating film; and

patterning the control gate film to form a control gate pattern.