Parallel operational processing device

• US 20070180006A1
• Filed: 01/26/2007
• Published: 08/02/2007
• Est. Priority Date: 01/31/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Noda, Hideyuki, Gyoten, Takayuki, Dosaka, Katsumi, Tanizaki, Tetsushi
• Granted Patent: US 7,505,352 B2
• Time in Patent Office: Days
• US Class Current: 708/200
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.

Claims

1. A parallel operational processing device comprising:

a plurality of memory blocks each including (i) a plurality of memory cells arranged in rows and columns, and (ii) a plurality of bit lines arranged corresponding to the respective memory cell columns;

a plurality of operational processing units, arranged between said plurality of memory blocks, each having a plurality of operation units each for executing a processing operation on received data; and

data transfer circuitry including a plurality of data write/read circuits, arranged alternately on opposite sides of the bit lines in each memory block, each for transferring data with an operational unit of an adjacent operational processing unit, a memory block being shared between adjacent operational processing units.

2. The parallel operational processing device according to claim 1, wherein

said plurality of memory blocks are divided into a plurality of memory mats each including the memory blocks aligned in one direction, and

said parallel operational processing device further comprises local control circuits arranged in a region between the memory mats, for controlling operations of the data transfer circuitry and of the operational processing units .

3. The parallel operational processing device according to claim 1, wherein

each of the memory blocks further includes a plurality of word lines arranged corresponding to the respective memory cell rows,

the data write/read circuits of each data transfer circuit transfer data between corresponding bit lines and corresponding operational units, and

the memory blocks arranged at opposite ends among said plurality of memory blocks each are halved in number of the word lines as compared with other memory block shared by the adjacent operational processing units.

4. The parallel operational processing device according to claim 3, wherein

the data transfer circuitry includes data write/read circuits arranged on first sides of the bit lines of the memory block arranged at each end of the opposite ends, and being coupled to a common, adjacent operational processing unit.

5. The parallel operational processing device according to claim 1, wherein

each of the memory blocks has a plurality of word lines arranged corresponding to the respective memory cell rows;

and

said parallel operational processing device further comprises a plurality of local control circuits arranged corresponding to said operational processing units, and controlling operations of corresponding data write/read circuits of the data transfer circuitry and the corresponding operational processing units,

the local control circuit, provided for the data write/read circuits arranged corresponding to a memory block storing a result of processing operation, controlling the corresponding memory block and corresponding data write/read circuits such that the corresponding write/read circuits execute sequentially reading and writing of data with the corresponding operational unit while holding a word line in the corresponding memory block in a selected state in a data accessing cycle.

6. The parallel operational processing device according to claim 5, wherein

the operational processing units have a processing cycle determined by a clock signal, and

the local control circuits each produce and supply a data read activating signal and a data write activating signal to corresponding data write/read circuits for controlling operations of said corresponding data write/read circuits asynchronously with said clock signal, in accordance with an operation mode instructing signal.