Method and apparatus for implementing transfer ordering using hardware linked list

• US 20070180155A1
• Filed: 02/01/2006
• Published: 08/02/2007
• Est. Priority Date: 02/01/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Irish, John
• Application Number:
  US11/344,905
• Publication Number:
  US 20070180155A1
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A method and apparatus are provided for implementing transfer ordering in a processor input/output (I/O) interface. A pointer field is added to a command buffer. Commands are chained together in a linked list defining the transfer ordering. A currently executing command, or a command whose data is currently being transferred is held in a current execution register. The current execution register includes a pointer to the next command to be executed, or data to be transferred. When the current command completes, the pointer is used to fetch information for a next command. A command that last received an ordering event is held in a last received register. The last received register contains a link pointer field, which initially is not valid. When the next ordering event occurs, the link pointer field is loaded with a pointer to the command corresponding to the new ordering event. The register information is then written to the command buffer.

Claims

1. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface comprising:

a command buffer for storing a plurality of command entries, each command entry for storing a linked list pointer to a next command, and a linked list of commands being chained together by said linked list pointers for defining the transfer ordering;

a current execution register storing a currently executing command;

said current execution register for storing a pointer to the next command to be executed, and said pointer being used to fetch information for the next command when the current command completes; and

a last received register storing a last received command until an ordering event occurs;

said last received register for storing a pointer to a command corresponding to the new ordering event when the next ordering event occurs.

2. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein said current execution register further stores a current command having data currently being transferred.

3. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein said current execution register stores a pointer to a next command having data to be transferred.

4. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein information for the last received register is written to the command buffer when the next ordering event occurs.

5. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 4 wherein the information written includes the linked list pointer to the next command and an indicator that the ordering event for this command has occurred, whereby writing the linked list pointer to the command buffer is provided with a required write to update the status indicator.

6. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein a separate command status buffer is provided;

and each said linked list pointer to a next command is stored in said command status buffer.

7. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein the command corresponding to the ordering event is moved directly to the current execution register and no link is created when the ordering linked list is empty and the current execution register is empty when an ordering event occurs.

8. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein the command corresponding to the ordering event is stored in the last received register when the ordering linked list is empty and the current execution register contains a valid command when an ordering event occurs.

9. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 8 wherein a sequence of operations completed when an ordering event occurs further includes the pointer in the current execution register being updated to point to the command in the last received register.

10. Apparatus for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 1 wherein the command from the last received register is moved directly to the current execution register when the current command completes and the pointer in the current execution register is pointing to the command in the last received register.

11. A method for implementing transfer ordering in a processor input/output (I/O) interface comprising the step of:

storing a plurality of command entries in a command buffer and storing a linked list pointer to a next command in each stored command entry to chain together a linked list of commands by said linked list pointers for defining the transfer ordering;

storing a currently executing command in a current execution register and storing a pointer to the next command to be executed in said current execution register, and said pointer being used to fetch information for the next command when the current command completes; and

storing a last received command in a last received register until an ordering event occurs; and

storing a pointer in said last received register to a command corresponding to the new ordering event when the next ordering event occurs.

12. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising storing a current command having data currently being transferred in said current execution register.

13. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising storing a pointer to a next command having data to be transferred in said current execution register.

14. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising writing information for the last received register to the command buffer when the next ordering event occurs.

15. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 14 wherein said writing information includes writing the linked list pointer to the next command and writing an indicator that the ordering event for this command has occurred, whereby writing the linked list pointer to the command buffer is provided with a required write to update the status indicator.

16. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising providing a separate command status buffer for storing command status information;

and wherein each said linked list pointer to a next command is stored in said command status buffer.

17. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising moving the command corresponding to the ordering event directly to the current execution register without creating a link when the ordering linked list is empty and the current execution register is empty when the ordering event occurs.

18. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising storing the command corresponding to the ordering event in the last received register when the ordering linked list is empty and the current execution register contains a valid command when an ordering event occurs, and updating the pointer in the current execution register to point to the command in the last received register.

19. A method for implementing transfer ordering in a processor input/output (I/O) interface as recited in claim 11 further comprising moving the command from the last received register directly to the current execution register when the current command completes and the pointer in the current execution register is pointing to the command in the last received register.