Semiconductor device and control method therefor

• US 20070180184A1
• Filed: 12/07/2006
• Published: 08/02/2007
• Est. Priority Date: 12/13/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Ogawa, Akira, Yano, Masaru, Sakashita, Mototada, Nakai, Tsutomu
• Granted Patent: US 7,450,419 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2263 Write conditionally, e.g. only if new data and old data differ

Abstract

The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.

Claims

1. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a detection circuit detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array and comparing the number of bits with a predetermined number of bits;

a latch circuit latching inversion data, which is either the division data inverted or not inverted in accordance with a result of comparing the number of bits with the predetermined number of bits;

a write circuit coupled to the latch circuit and programming the inversion data into the memory cell array; and

a control circuit coupled to the detection circuit, the latch circuit, and the write circuit to cause the detection circuit to detect the number of bits to be written as next division data and to compare the number of bits of the next division data with the predetermined number of bits, while concurrently controlling the write circuit to program the inversion data into the memory cell array.

2. The semiconductor device as claimed in claim 1, further comprising an index latch circuit latching index data indicative of whether the inversion data is the division data inverted or not inverted,

wherein the detection circuit outputs the index data to the index latch circuit in response to the result of comparing the number of bits with the predetermined number of bits;

and

wherein the write circuit programs the index data from the index latch circuit into the memory cell array, while programming the inversion data into the memory cell array.

3. The semiconductor device as claimed in claim 1 or 2, further comprising a switch circuit transferring the inversion data to the latch circuit;

wherein the switch circuit is switched off, while the detection circuit is detecting the number of bits to be written as the division data and comparing the number of bits with the predetermined number of bits, and the switch circuit is switched on, while transferring the inversion data to the latch circuit.

4. The semiconductor device as claimed in any of claims 1 to 3, further comprising a storage device storing the data to be programmed, the data being received from an external circuit, and outputting the division data to the detection circuit and the latch circuit.

5. The semiconductor device as claimed in any of claims 1 to 4,

wherein the write circuit pre-charges a bit line to be connected to one of the plurality of memory cells in the memory cell array, into which the inversion data is to be programmed, before programming the inversion data into the memory cell array, and

wherein the control circuit controls the detection circuit to detect the number of bits to be written as next division data and to compare the number of bits of the next division data with the predetermined number of bits, while the write circuit is precharging the bit line.

6. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a detection circuit detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array and comparing the number of bits with a predetermined number of bits;

a latch circuit latching inversion data, which is either the division data inverted or not inverted in accordance with a result of comparing the number of bits with the predetermined number of bits; and

a write circuit coupled to the latch circuit and programming the inversion data into the memory cell array,

wherein the latch circuit includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits.

7. The semiconductor device as claimed in claim 6,

wherein the latch circuit further includes a circuit having two inverter circuits connected circularly;

and

wherein each of the pair of nodes is respectively arranged between the two inverter circuits.

8. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a read circuit reading division data that is divided from data to be read from the memory cell array;

a control circuit determining whether index data indicates that the division data is inverted or not inverted when the division data is programmed; and

a latch circuit latching the division data read by the read circuit and outputting inversion data that is either the division data inverted or not inverted in accordance with a result of determining whether the index data indicates that the division data is inverted or not inverted,

wherein the read circuit reads next division data from the memory cell array, while the control circuit is determining whether the index data indicates that the division data is inverted or not inverted.

9. The semiconductor device as claimed in claim 8, further comprising a storage device storing the inversion data output from the latch circuit and outputting the data to be read from the memory cell array, including the inversion data, to an external circuit.

10. The semiconductor device as claimed in claim 8, further comprising an index latch circuit latching the index data, while the latch circuit is latching the division data,

wherein the read circuit reads the index data, while reading the division data from the memory cell array;

and

wherein the control circuit reads the index data from the index latch circuit and determines whether the index data indicative of whether the division data is inverted or not inverted when the division data is written, in response to the index data.

11. The semiconductor device as claimed in claim 10, further comprising a storage device storing the inversion data output from the latch circuit and outputting the data to be read from the memory cell array, including the inversion data, to an external circuit.

12. The semiconductor device as claimed in claim 10, further comprising a switch circuit transferring the division data to the latch circuit,

wherein the switch circuit is switched off, while the control circuit is determining whether the index data indicates that the division data is inverted or not inverted, and the switch circuit is switched on, while transferring the division data from the read circuit to the latch circuit.

13. The semiconductor device as claimed in claim 12, further comprising a storage device storing the inversion data output from the latch circuit and outputting the data to be read from the memory cell array, including the inversion data, to an external circuit.

14. A semiconductor device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a read circuit reading division data that is divided from data to be read from the memory cell array;

a control circuit determining whether index data indicates that the division data is inverted or not inverted when the division data is programmed; and

a latch circuit latching the division data read by the read circuit and outputting inversion data that is either the division data inverted or that not inverted in accordance with a result of determining whether the index data indicates that the division data is inverted or not inverted,

wherein the latch circuit includes a pair of nodes operating in a complementary manner, and outputs the inversion data that is either the division data inverted or not inverted by outputting the division data from either of the pair of nodes in response to the index data.

15. The semiconductor device as claimed in claim 14,

wherein the latch circuit further includes a circuit having two inverter circuits connected circularly;

and

wherein each of the pair of nodes is respectively arranged between the two inverter circuits.

16. A method for controlling a semiconductor device comprising a memory cell array having a plurality of nonvolatile memory cells, the method comprising:

detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

comparing the number of bits with a predetermined number of bits;

inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits; and

programming the inversion data into the memory cell array,

wherein detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.

17. A method for controlling a semiconductor device comprising a memory cell array having a plurality of nonvolatile memory cells, the method comprising:

reading division data that is divided from data to be read from the memory cell array;

determining whether index data indicates that the division data is inverted or not inverted when the division data is programmed; and

inverting or not inverting the division data in accordance with a result of determining whether the index data indicates that the division data is inverted or not inverted,

wherein reading next division data from the memory cell array, while determining whether the index data indicates that the division data is inverted or not inverted.

18. A wireless communications device, comprising:

a flash memory comprising;

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data and the comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, while the programming portion is concurrently programming the inversion data into the memory cell array;

a processor;

a communications component;

a transmitter;

a receiver; and

an antenna connected to the transmitter circuit and the receiver circuit.

19. The wireless communications device of claim 18, wherein said flash memory is NAND flash memory.

20. The wireless communications device of claim 18, wherein said flash memory is NOR flash memory.

21. The wireless communications device of claim 18, wherein said flash memory comprises at least one memory cell operable to store more than one bit.

22. A computing device comprising:

a processor;

an input component;

an output component;

a memory comprising;

a volatile memory; and

a flash memory comprising;

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data and the comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, while the programming portion is concurrently programming the inversion data into the memory cell array.

23. The computing device of claim 22, wherein said computing device is a personal computer (PC).

24. The computing device of claim 22, wherein said computing device is a personal digital assistant (PDA).

25. The computing device of claim 22, wherein said computing device is a gaming system.

26. A portable media player comprising:

a processor;

a cache;

a user input component;

a coder-decoder component; and

a memory comprising;

a flash memory comprising;

a memory cell array;

a bit detection portion for detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array;

a bit comparison portion for comparing the detected number of bits with a predetermined number of bits;

an inversion portion for inverting the division data to produce inversion data in accordance with a result of comparing the detected number of bits with the predetermined number of bits; and

a programming portion for programming the inversion data into the memory cell array;

wherein the bit detection portion is further operable to detect the number of bits to be written as next division data and the comparison portion is further operable to compare the number of bits of next division data with the predetermined number of bits, while the programming portion is concurrently programming the inversion data into the memory cell array.

27. The portable media player of claim 26, wherein said portable media player is a portable music player.

28. The portable media player of claim 26, wherein said portable media player is a portable video player.