Electrical idle detection circuit including input signal rectifier

• US 20070180281A1
• Filed: 02/02/2006
• Published: 08/02/2007
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Ravezzi, Luca, Partovi, Hamid, Gopalakrishnan, Karthik
• Granted Patent: US 7,813,289 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

Claims

1. An electrical idle detection circuit, comprising:

a full wave rectifier configured to receive differential input signals and provide a rectified output signal based on the differential input signals; and

a first amplifier configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal and to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

2. The electrical idle detection circuit of claim 1, comprising:

a low pass filter configured to filter the rectified output signal and provide a filtered rectified output signal, wherein the first input signal includes the filtered rectified output signal.

3. The electrical idle detection circuit of claim 1, wherein the full wave rectifier comprises:

a second amplifier configured to receive the differential input signals and provide differential output signals; and

a transistor pair configured to receive the differential output signals and provide the rectified output signal.

4. The electrical idle detection circuit of claim 3, wherein the second amplifier is configured to have a bandwidth greater than one half the data rate of the differential input signals and the transistor pair is configured to provide a high voltage to current gain.

5. The electrical idle detection circuit of claim 3, comprising:

a common mode feedback circuit configured to average the differential output signals and provide a bias voltage, wherein the second amplifier receives the bias voltage and adjusts common mode levels in the differential output signals based on the bias voltage.

6. The electrical idle detection circuit of claim 5, wherein the common mode feedback circuit is configured to adjust the bias voltage to a threshold voltage of the transistor pair.

7. The electrical idle detection circuit of claim 5, wherein the common mode feedback circuit comprises:

a resistor network configured to provide a common mode output voltage; and

a third amplifier configured to compare the common mode output voltage and a reference voltage to provide the bias voltage.

8. The electrical idle detection circuit of claim 1, comprising:

a hysterisis circuit configured to shift the reference signal to avoid multiple transitions of the output signal upon entry into and exit out of electrical idle.

9. An electrical idle detection circuit, comprising:

a common mode difference detector configured to receive differential input signals and reduce common mode voltage noise in the differential input signals to provide a filtered common mode voltage and to provide common mode differential output signals based on the filtered common mode voltage;

a first switch controlled via one of the common mode differential output signals to shift a first input signal;

a second switch controlled via another one of the common mode differential output signals to shift a second input signal that is based on a reference signal; and

a first amplifier configured to receive the first input signal and the second input signal and to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

10. The electrical idle detection circuit of claim 9, wherein the common mode difference detector comprises:

a resistor network configured to provide a common mode voltage;

a filter configured to low pass filter the common mode voltage to provide the filtered common mode voltage; and

a transistor pair configured to receive the filtered common mode voltage and a common mode reference signal and to provide the common mode differential output signals.

11. The electrical idle detection circuit of claim 9, comprising:

a hysterisis circuit configured to shift the reference signal to avoid multiple transitions of the output signal upon entry into and exit out of electrical idle.

12. The electrical idle detection circuit of claim 9, comprising a full wave rectifier configured to receive the differential input signals and provide a rectified output signal based on the differential input signals, wherein the first input signal is based on the rectified output signal.

13. The electrical idle detection circuit of claim 12, comprising:

a low pass filter configured to filter the rectified output signal and provide a filtered rectified output signal, wherein the first input signal includes the filtered rectified output signal.

14. The electrical idle detection circuit of claim 12, wherein the full wave rectifier comprises:

a second amplifier configured to receive the differential input signals and provide differential output signals; and

a transistor pair configured to receive the differential output signals and provide the rectified output signal.

15. The electrical idle detection circuit of claim 14, comprising:

a common mode feedback circuit configured to average the differential output signals and provide a bias voltage, wherein the second amplifier receives the bias voltage and adjusts common mode levels in the differential output signals based on the bias voltage.

16. An electrical idle detection circuit, comprising:

means for rectifying differential input signals to provide a rectified output signal based on the differential input signals; and

means for comparing a first input signal that is based on the rectified output signal and a second input signal that is based on a reference signal to provide an output signal that indicates the differential input signals are one of active and in electrical idle.

17. The electrical idle detection circuit of claim 16, comprising:

means for reducing common mode voltage noise in the differential input signals to provide a filtered common mode voltage;

means for outputting differential output signals based on the filtered common mode voltage;

means for shifting the first input signal via one of the differential output signals; and

means for shifting the second input signal via another one of the differential output signals.

18. The electrical idle detection circuit of claim 16, comprising:

means for filtering the rectified output signal to provide a filtered rectified output signal in the first input signal.

19. The electrical idle detection circuit of claim 16, comprising:

means for averaging differential output signals to provide a bias voltage based on a common mode voltage of the differential output signals, and wherein the means for rectifying comprises;

means for comparing the differential input signals to provide the differential output signals and adjust the common mode voltage of the differential output signals via the bias voltage.

20. The electrical idle detection circuit of claim 16, comprising:

means for shifting the reference signal to avoid multiple transitions of the output signal upon entry into and exit out of electrical idle.

21. A method for detecting electrical idle in a communications bus, comprising:

rectifying differential input signals to provide a rectified output signal based on the differential input signals; and

comparing a first input signal that is based on the rectified output signal and a second input signal that is based on a reference signal to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

22. The method of claim 21, comprising:

reducing common mode voltage noise of the differential input signals to provide a filtered common mode voltage of the differential input signals;

outputting differential output signals based on the filtered common mode voltage;

shifting the first input signal via one of the differential output signals; and

shifting the second input signal via another one of the differential output signals.

23. The method of claim 21, comprising:

averaging differential output signals to provide a bias voltage based on a common mode voltage of the differential output signals, and wherein rectifying differential input signals comprises;

comparing the differential input signals to provide the differential output signals and adjust the common mode voltage of the differential output signals via the bias voltage.

24. The method of claim 21, comprising:

filtering the rectified output signal to provide a low pass filtered rectified output signal in the first input signal; and

shifting the reference signal to avoid multiple transitions of the output signal upon entry into and exit out of electrical idle.

25. A method for detecting electrical idle in a communications bus, comprising:

reducing common mode voltage noise in differential input signals to provide a filtered common mode voltage;

outputting differential output signals based on the filtered common mode voltage;

shifting a first input signal via one of the differential output signals;

shifting a second input signal via another one of the differential output signals; and

comparing the first input signal and the second input signal to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

26. The method of claim 25, wherein reducing common mode voltage noise comprises:

averaging the differential input signals to provide a common mode voltage; and

filtering the common mode voltage to provide the filtered common mode voltage.

27. The method of claim 26, wherein outputting differential output signals comprises:

comparing the filtered common mode voltage and a common mode reference signal to provide the differential output signals.

28. The method of claim 25, comprising:

rectifying the differential input signals to provide a rectified output signal; and

filtering the rectified output signal to provide a filtered rectified output signal in the first input signal.

29. The method of claim 25, comprising:

shifting a reference signal in the second input signal to avoid multiple transitions of the output signal upon entry into and exit out of electrical idle.