Semiconductor memory device and method of fabricating the same

• US 20070181969A1
• Filed: 02/09/2007
• Published: 08/09/2007
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Jeong-ho, Ahn, Jong-hyun, Kim, Kwang-duk
• Granted Patent: US 7,649,240 B2
• Time in Patent Office: Days
• US Class Current: 257/529
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A semiconductor memory device having an improved fuse structure may include an interlayer insulating film on a semiconductor substrate, an opening in the interlayer insulating film, a vertical fuse that may conform to the opening, a fuse insulating film on the vertical fuse that may fill the opening, and metal wiring lines that may be electrically connected to the vertical fuse.

Claims

1. A semiconductor memory device, comprising:

an interlayer insulating film on a semiconductor substrate;

an opening in the interlayer insulating film;

a vertical fuse conforming to the opening;

a fuse insulating film on the vertical fuse, the fuse insulating film filling the opening; and

a metal wiring line electrically connected to the vertical fuse.

2. The semiconductor memory device as claimed in claim 1, wherein the vertical fuse comprises a metal or a metal nitride.

3. The semiconductor memory device as claimed in claim 1, wherein the vertical fuse comprises Ti, TiN, Ta, TaN, or Al.

4. The semiconductor memory device as claimed in claim 1, wherein the fuse insulating film comprises a material having a larger selectivity ratio than the interlayer insulating film.

5. The semiconductor memory device as claimed in claim 4, wherein the interlayer insulating film comprises a high density plasma oxide film.

6. The semiconductor memory device as claimed in claim 4, wherein the fuse insulating film comprises a flowable oxide film, a tonen silazene film, a spin-on-glass film, an undoped silica glass film, a tetraethyl ortho silicate film, or a low temperature oxide film.

7. The semiconductor memory device as claimed in claim 1, wherein the metal wiring line comprises Cu or W.

8. The semiconductor memory device as claimed in claim 1, further comprising a barrier metal film that conforms to the metal wiring line and the opening.

9. The semiconductor memory device as claimed in claim 1, wherein the metal wiring line is on the vertical fuse and the fuse insulating film.

10. The semiconductor memory device as claimed in claim 1, wherein the fuse insulating film fills a portion of the opening.

11. The semiconductor memory device as claimed in claim 10, wherein the metal wiring line fills a portion of the opening that the fuse insulating film does not fill, so that the metal wiring line is in contact with a portion of the side of the vertical fuse.

12. A method of fabricating a semiconductor memory device, the method comprising:

forming an interlayer insulating film on a semiconductor substrate;

forming an opening in the interlayer insulating film;

forming a conductive film on the opening and the interlayer insulating film, the conductive film conforming to the opening and the interlayer insulating film;

forming a fuse insulating film on the conductive film to fill the opening;

forming a vertical fuse in the opening by removing the conductive film and the fuse insulating film on the interlayer insulating film; and

forming a metal wiring line that electrically connects to the vertical fuse.

13. The method as claimed in claim 12, wherein the vertical fuse comprises a metal or a metal nitride.

14. The method as claimed in claim 12, wherein the vertical fuse comprises Ti, TiN, Ta, TaN, or Al.

15. The method as claimed in claim 12, wherein the fuse insulating film comprises a material having a larger selectivity ratio than the interlayer insulating film.

16. The method as claimed in claim 15, wherein the interlayer insulating film comprises a high density plasma oxide film.

17. The method as claimed in claim 15, wherein the fuse insulating film comprises a flowable oxide film, a tonen silazene film, a spin-on-glass film, an undoped silica glass film, a tetraethyl ortho silicate film, or a low temperature oxide film.

18. The method as claimed in claim 12, wherein the metal wiring line comprises Cu or W.

19. The method as claimed in claim 12, further comprising forming a barrier metal film between the metal wiring line and the opening such that the barrier metal film conforms to the metal wiring line and the opening.

20. The method as claimed in claim 12, wherein the removal of the conductive film and the fuse insulating film on the interlayer insulating film comprises chemical mechanical polishing.

21. The method as claimed in claim 20, wherein during the chemical mechanical polishing, the fuse insulating film in an upper part of the opening is partially removed.

22. The method as claimed in claim 21, wherein the metal wiring line fills the opening where the fuse insulating film was partially removed, so that the metal wiring line is in contact with a portion of the side of the vertical fuse and the opening.