Trench-gate transistors and their manufacture

• US 20070181975A1
• Filed: 02/28/2005
• Published: 08/09/2007
• Est. Priority Date: 03/10/2004
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Koops, Gerrit, In 'T Zandt, Michael
• Granted Patent: US 7,361,555 B2
• Time in Patent Office: Days
• US Class Current: 257/559
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate transistor (1) has an integral first layer of silicon dioxide (31) which extends from the upper surface (10a) of the semiconductor body (10) over top corners of each cell array trench (20), the integral first layer also providing a thin gate dielectric insulating layer (31A) for a thick gate electrode (41) and the integral first layer also providing a first part (31B) of a stack of materials which constitute a thick trench sidewall insulating layer (31B,32,33) for a thin field plate (42), a layer of silicon nitride (32) providing a second part of the stack and a second layer of silicon dioxide (33) providing a third part of the stack. The integrity of the first silicon dioxide layer (31) over the trench (20) top corners helps to avoid gate (41)—source (24) short circuits. In a method of manufacture (FIGS. 2A to 2F) a hardmask (21) used to etch the trenches (20) is removed before providing the silicon dioxide layer (31), which layer (31) is then protected by successive selective etching of the oxide layer (33) and the nitride layer (32) in the upper parts of the trenches (20). After the gate electrodes (41) are provided, layers for the channel accommodating regions (23) and source regions (24) may be formed through the oxide layer (31) on the upper surface (10a).

Claims

1. A cellular trench-gate transistor comprising a silicon semiconductor body having an array of transistor cells (TC),

the cells being bounded by a pattern of array trenches lined with insulating material within the array, the array trenches extending from an upper surface of the semiconductor body through a channel accommodating body region into an underlying drain drift region,

the insulating material in each array trench providing a thin gate dielectric insulating layer on a trench sidewall adjacent the channel accommodating body region and a thick insulating layer on a trench sidewall adjacent the drain drift region,

conductive material in each array trench providing a gate electrode on the thin trench sidewall insulating layer and a field plate on the thick trench sidewall insulating layer,

wherein an integral first layer of silicon dioxide extends from the upper surface of the semiconductor body over top corners of each array trench,

the integral first layer also providing the thin gate dielectric insulating layer and the integral first layer also providing a first part of a stack of materials which constitute the thick trench sidewall insulating layer,

a layer of silicon nitride providing a second part of the stack, and

a second layer of silicon dioxide providing a third part of the stack.

2. A transistor as claimed in claim 1,

wherein an edge termination for the transistor includes a perimeter trench around the array of transistor cells (TC),

wherein the stack of materials which constitutes the thick trench sidewall insulating layer in the array trenches extends around a top corner of the perimeter trench and on to the upper surface of the semiconductor body, and

wherein conductive material on the stack in the perimeter trench extends around the top corner of the perimeter trench to provide an edge field plate for the transistor.

7. A transistor as recited in claim 1, wherein

the drain drift region is more highly doped near the base of the array trenches than near the channel accommodating body region.

8. A transistor as recited in claim 2, wherein

the drift region is more highly doped near the base of the array trenches than near the channel accommodating body region.

3. A method of manufacturing a cellular trench-gate transistor comprising a silicon semiconductor body having an array of transistor cells (TC), the cells being bounded by a pattern of array trenches lined with insulating material within the array, the array trenches extending from an upper surface of the semiconductor body through a channel accommodating body region into an underlying drain drift region, the insulating material in each array trench providing a thin gate dielectric insulating layer on a trench sidewall adjacent the channel accommodating body region and a thick insulating layer on a trench sidewall adjacent the drain drift region, conductive material in each array trench providing a gate electrode on the thin trench sidewall insulating layer and a field plate on the thick trench sidewall insulating layer, wherein the method includes the steps of:

(a) providing a hardmask on the upper surface of the semiconductor body, then forming the array trenches by etching using the hardmask, and then removing the hardmask;

(b) providing an integral first layer of silicon dioxide which extends on the upper surface of the semiconductor body, over the top corners of the array trenches and over the sidewalls and the base of each of the array trenches, the first layer of silicon dioxide providing the thin gate dielectric insulating layer in the manufactured transistor;

(c) providing a layer of silicon nitride over the first layer of silicon dioxide and then providing a second layer of silicon dioxide over the silicon nitride layer;

(d) providing conductive material in each array trench to form the thin field plate;

(e) selectively etching the second silicon dioxide layer and then the silicon nitride layer above the thin field plates such that the thick trench sidewall insulating layer has a stack of the first silicon dioxide layer, the silicon nitride layer and the second silicon dioxide layer; and

then

(f) providing conductive material in each array trench to form the thick gate electrode.

4. The method as recited in claim 3, wherein the hardmask used in step (a) is a single silicon dioxide layer.

5. The method as recited in claim 3, including the further step of:

(g) forming layers for the channel accommodating body region and source regions for the transistor cells through the first layer of silicon dioxide on the upper surface of the semiconductor body.

6. The method as recited in claim 3, wherein steps for forming an edge termination for the transistor include:

(h) forming a perimeter trench around the array of transistor cells (TC) during step (a) and using the same hardmask;

(i) providing the first layer of silicon dioxide, the layer of silicon nitride and second layer of silicon dioxide around a top corner of the perimeter trench and on to the upper surface at the edge of the semiconductor body during steps (b) and (c);

(j) providing conductive material in the perimeter trench by means of step (d);

(k) allowing the stack of the first silicon dioxide layer, the silicon nitride layer and the second silicon dioxide layer to remain around a top corner of the perimeter trench and on the upper surface at the edge of the semiconductor body during the selective etching of step (e); and

(I) providing conductive material on the stack around the top corner of the perimeter trench to provide an edge field plate for the transistor at the same time as forming the thick gate electrode in the array trenches during step (f).

9. A transistor manufacture by the method as recited in claim 3, wherein

the drift region is more highly doped near the base of the array trenches than near the channel accommodating body region.