Voltage regulator in semiconductor memory device
First Claim
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1. A voltage regulator, comprising:
- a level down shifter reducing a high voltage;
a voltage divider dividing the reduced high voltage to generate a first division result;
a comparator comparing a reference voltage to the first division result to generate a comparison result; and
a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider,wherein the voltage divider divides the output voltage to generate a second division result, the second division result being fed back as a control voltage signal to the level down shifter.
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Abstract
Provided is a voltage regulator. The voltage regulator includes a level down shifter reducing an applied high voltage, a voltage divider dividing the reduced high voltage to generate a first division result, a comparator comparing a reference voltage to the first division result, and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider. The voltage divider divides the output voltage to generate a second division result serving as a voltage control signal fed back to the level down shifter.
13 Citations
20 Claims
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1. A voltage regulator, comprising:
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a level down shifter reducing a high voltage; a voltage divider dividing the reduced high voltage to generate a first division result; a comparator comparing a reference voltage to the first division result to generate a comparison result; and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider, wherein the voltage divider divides the output voltage to generate a second division result, the second division result being fed back as a control voltage signal to the level down shifter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A voltage regulator generating an output voltage at an output terminal, comprising:
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a level down shifter reducing a high voltage; a switch receiving the reduced high voltage and an enable signal; a first driver gated by an output of the switch to output the reduced high voltage; a second driver gated by the output of the first driver to output the reduced high voltage as the output voltage at the output terminal; a ripple eliminator connected between the output of the first driver and the output terminal; a voltage divider dividing the output voltage provided by the second driver to generate a first division result and a second division result; and a comparator comparing a reference voltage to the first division result to generate a comparison result, wherein the second driver generates the output voltage in relation to the comparison result voltage divider, and wherein the second division result is fed back as a control voltage signal to the level down shifter. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification