Level shifter for flat panel display device

• US 20070182448A1
• Filed: 11/17/2006
• Published: 08/09/2007
• Est. Priority Date: 01/20/2006
• Status: Abandoned Application

• Current Assignee: Byong Deok Choi, Oh Kyong Kwon
• Original Assignee: Byong Deok Choi, Oh Kyong Kwon
• Inventors: Kwon, Oh Kyong, Choi, Byong Deok
• Application Number:
  US11/601,479
• Publication Number:
  US 20070182448A1
• Time in Patent Office: Days
• US Class Current: 326/68
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A level shifter for a flat panel display device is provided. The level shifter includes a first transistor coupled with a first power supply and having a gate and a drain are coupled together; and a capacitor coupled between an input voltage terminal and a first node coupled with the drain of the first transistor. The level shifter also includes a second transistor coupled with the first node to reset the capacitor; and a third transistor coupled to the first node, and coupled between a second power supply and an output voltage terminal. The level shifter also includes a fourth transistor to the first node, and coupled between an inverse input voltage terminal and the output voltage terminal.

Claims

1. A level shifter for a flat panel display device, the level shifter comprising:

a first transistor coupled with a first power supply, the first transistor having a gate and a drain that are coupled together;

a capacitor coupled between an input voltage terminal and a first node coupled with the drain of the first transistor;

a second transistor coupled with the first node and adapted to reset the capacitor;

a third transistor having a gate coupled to the first node, wherein the third transistor is coupled between a second power supply and an output voltage terminal; and

a fourth transistor having a gate coupled to the first node, wherein the fourth transistor is coupled between an inverse input voltage terminal and the output voltage terminal.

2. The level shifter for a flat panel display device according to claim 1, wherein the first transistor is a diode-connected P-channel transistor or an N-channel transistor.

3. The level shifter for a flat panel display device according to claim 1, wherein the second transistor comprises:

a gate adapted to receive a reset pulse;

a source coupled to a ground; and

a drain coupled to the first node.

4. The level shifter for a flat panel display device according to claim 1, wherein the third transistor and the fourth transistor are different types of transistors.

5. The level shifter for a flat panel display device according to claim 4, wherein:

a source of the third transistor is coupled to the second power supply;

a source of the fourth transistor is coupled to the inverse input voltage terminal; and

a drain of the third transistor and a drain of the fourth transistor are coupled to the output voltage terminal.

6. The level shifter for a flat panel display device according to claim 1, wherein the second power supply has a voltage value that is about twice that of the first power supply.

7. A level shifter for a flat panel display device, the level shifter comprising:

a first transistor coupled with a ground voltage or a power supply, and having a gate and a drain coupled together;

a capacitor coupled between an input voltage terminal and a first node coupled with the drain of the first transistor;

a second transistor coupled between the first node and the ground voltage or the power supply to reset the capacitor;

a third transistor having a gate coupled to the first node, wherein the third transistor is coupled between the power supply and an output voltage terminal; and

a fourth transistor having a gate coupled to the first node, wherein the fourth transistor is coupled between an inverse input voltage terminal and the output voltage terminal.

8. The level shifter for a flat panel display device according to claim 7, wherein the first transistor is a diode-connected N-channel transistor or a P-channel transistor.

9. The level shifter for a flat panel display device according to claim 7, wherein the second transistor comprises:

a gate adapted to receive a reset pulse;

a source coupled with the ground voltage or the power supply; and

a drain coupled to the first node.

10. The level shifter for a flat panel display device according to claim 7, wherein the third transistor and the fourth transistor are different types of transistors.

11. The level shifter for a flat panel display device according to claim 10, wherein:

a source of the third transistor is coupled to the power supply;

a source of the fourth transistor is coupled to the inverse input voltage terminal; and

a drain of the third transistor and a drain of the fourth transistor are coupled to the output voltage terminal.

12. The level shifter for a flat panel display device according to claim 7, wherein the power supply has a negative voltage value.

13. A level shifter for a flat panel display device, the level shifter comprising:

an initial charging part; and

a plurality of level shifter parts individually coupled with the initial charging part,

wherein each of the plurality of level shifter parts comprises;

a first transistor having a gate adapted to receive a signal output from the initial charging part;

a capacitor coupled between an input voltage and a first node to which a drain of the first transistor is coupled;

a second transistor having a gate coupled to the first node, wherein the second transistor is coupled between a first power supply and an output voltage terminal; and

a third transistor having a gate coupled to the first node, wherein the third transistor is coupled between an inverse input voltage terminal and the output voltage terminal.

14. The level shifter for a flat panel display device according to claim 13, wherein a source of the first transistor is coupled to a second power supply.

15. The level shifter for a flat panel display device according to claim 13, wherein the second power supply outputs a positive voltage lower than that of the first power supply.

16. The level shifter for a flat panel display device according to claim 13, wherein the second transistor and the fourth transistor are different types of transistors.

17. The level shifter for a flat panel display device according to claim 16, wherein:

a source of the third transistor is coupled to the first power supply;

a source of the fourth transistor is coupled to the inverse input voltage terminal; and

a drain of the third transistor and a drain of the fourth transistor are coupled to the output voltage terminal.

18. The level shifter for a flat panel display device according to claim 13, wherein the initial charging part comprises:

a level-up circuit part for receiving a reset signal and an inverse reset signal to level up to a predetermined voltage and output the reset signal and the inverse reset signal; and

a buffer part for stabilizing an output voltage of the level-up circuit part.

19. The level shifter for a flat panel display device according to claim 18, wherein the level-up circuit part comprises:

a first N-channel transistor and a second N-channel transistor for receiving the reset signal and the inverse reset signal; and

a latch circuit for leveling up the input voltage, wherein the latch circuit comprises a first P-channel transistor and a second P-channel transistor.

20. A level shifter for a flat panel display device, the level shifter comprising:

an initial charging part; and

a plurality of level shifter parts individually coupled with the initial charging part,

wherein each of the plurality of level shifter parts comprises;

a first transistor having a gate adapted to receive a signal output from the initial charging part;

a capacitor coupled between an inverse input voltage terminal and a first node coupled to a drain of the first transistor;

a second transistor having a gate coupled to the first node, wherein the second transistor is coupled between a first power supply and an output voltage terminal; and

a third transistor having a gate coupled to the first node, wherein the third transistor is coupled between an input voltage terminal and the output voltage terminal.

21. The level shifter for a flat panel display device according to claim 20, wherein a source of the first transistor is coupled with the first power supply.

22. The level shifter for a flat panel display device according to claim 20, wherein the third transistor and the fourth transistor are different types of transistors.

23. The level shifter for a flat panel display device according to claim 22, wherein:

a source of the third transistor is coupled to the first power supply;

a source of the fourth transistor is coupled to the input voltage terminal; and

a drain of the third transistor and a drain of the fourth transistor are coupled to the output voltage terminal.

24. The level shifter for a flat panel display device according to claim 20, wherein the initial charging part comprises:

a level-up circuit part for receiving a reset signal and an inverse reset signal to level up to a predetermined voltage and output the reset signal and the inverse reset signal; and

a buffer part for stabilizing an output voltage of the level-up circuit part.

25. A level shifter for a flat panel display device, the level shifter comprising:

an initial charging part comprising;

a level-up circuit part for receiving a reset signal and an inverse reset signal to level up to a predetermined voltage and output the reset signal and the inverse reset signal; and

a buffer part for stabilizing an output voltage of the level-up circuit part; and

a plurality of level shifter parts individually coupled with the initial charging part,

wherein each of the plurality of level shifter parts comprises;

a first transistor having a gate adapted to receive a signal output from each of the initial charging parts, wherein the first transistor is coupled between a first node and a ground voltage or a power supply;

a capacitor coupled between the first node and an input voltage terminal or an inverse input voltage terminal;

a second transistor in which the gate is coupled to the first node, and wherein the second transistor is coupled between the power supply and an output voltage terminal; and

a third transistor having a gate coupled to the first node, and coupled at a first end between the inverse input voltage or the input voltage terminal and coupled at a second end to the output voltage terminal.