Resonant line drivers

• US 20070182461A1
• Filed: 05/12/2004
• Published: 08/09/2007
• Est. Priority Date: 05/12/2003
• Status: Abandoned Application

• Current Assignee: Midas Green Limited
• Original Assignee: Midas Green Limited
• Inventors: Harvey, Geoffrey
• Application Number:
  US10/556,418
• Publication Number:
  US 20070182461A1
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: H03K 19/0019 by energy recovery or adiabatic operation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

An electronic driver circuit for comnmunicating a logic value along a conductor (12) from one part of a system (10) to another (14) by representing each of two logic values by one of two logic levels (V_DD, V_ss).A capacitor (C_R1) reduces ground and power reference differences between a chip containing the driver and the board on which it is mounted. The capacitor also provides power and ground decoupling. According to another aspect, a controlled slew rate ramp initiates an incident or outbound wave or turn-on and circuits are described for this. The time taken to complete the controlled slew rate ramp can be adjusted. The arrangements allow reduced power consumption, whilst at the same time producing desirable signal characteristics.

Claims

1. An electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load, the circuit and conductor output signals respectively making corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level, inductance and capacitance of the conductor and the load producing resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition, the circuit comprising a ramp control circuit for controlling partial circuit output transitions between at least one of the pair of output voltage levels and the intermediate level to provide a substantially non-zero transition time for a partial circuit output transition.

2. A driver circuit according to claim 1 wherein the partial circuit output transition is controlled to be slow relative to other switching events in the circuit.

3. A driver circuit according to claim 1, further comprising a pull-up transistor and a pull-down transistor for pulling the circuit output up to a first of the two output voltage levels and down to a second of the two output voltage levels, wherein the partial circuit output transition is controlled to be slower than the switching of the pull-up and pull-down transistors.

4. A driver circuit according to claim 1, further comprising an intermediate level driving transistor which in switching-on drives the circuit output to the intermediate voltage level and in switching-off permits the circuit output to be driven to a first of the two output voltage levels, wherein the partial circuit output transition is controlled to be slower than the switching-off of the intermediate level driving transistor.

6. A driver circuit according to claim 1, wherein the partial circuit output transition time is controllable as a function of the time taken for the conductor output signal to substantially complete a conductor output transition.

7. A driver circuit according to claim 1 wherein the control circuitry comprises:

time-comparison circuitry for comparing the circuit output signal and the second control signal to determine whether the circuit output signal completes a circuit output transition before the second control signal completes the corresponding control transition; and

adjustment circuitry for adjusting the partial circuit transition time depending on the comparison.

8. A driver circuit according to claim 1, comprising reference ramp circuitry for generating a reference ramp, and comparator circuitry coupled to the reference ramp circuitry for comparing a partial circuit output transition with the reference ramp.

9. A driver circuit according to claim 8, wherein the comparator circuitry compares a level of the partial circuit output transition with a reference voltage that is approximately midway between the intermediate voltage level and an output voltage level to which the output is transitioning at a time approximately midway between a start of the partial circuit output transition and an expected completion of the partial circuit output transition.

10. A driver circuit according to claim 8, wherein the comparator circuitry comprises an integrating latching comparator to provide an average comparison between a partial circuit output transition and a signal representative of the reference ramp over substantially the whole time of the partial output transition.

12. A driver circuit according to claims 8, further comprising adjustment circuitry for adjusting the partial circuit transition time depending on the comparison.

13. A driver circuit according to claim 1, wherein the time taken for a partial circuit transition is controlled as a function of characteristics of at least one previous circuit output transition.

15. A driver according to claim 1, wherein the ramp control circuit comprises a source follower for driving the circuit output signal in a controlled manner.

16. A driver according to claim 1, comprising a switch connected between a source of the intermediate voltage level and the circuit output signal, wherein the ramp control circuit comprises a current mirror which supplies a current to the switch to drive the circuit output signal in a controlled manner.

19. An electronic driver circuit in accordance with claim 1, coupled between sources of different first, second, and third supply voltages, the second supply voltage lying between the first and third supply voltages, the circuit comprising:

control circuitry responsive to a circuit input signal for generating different first, second, and third control signals;

a first switch having (a) a first flow electrode coupled to the source of the first supply voltage, (b) a second flow electrode coupled to an output node from which a circuit output signal is provided, and (c) a control electrode responsive to the first control signal for controlling current flow between the first switch'"'"'s flow electrodes;

a second switch having (a) a first flow electrode coupled to the source of the second supply voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to the second control signal for controlling current flow between the second switch'"'"'s flow electrodes; and

a third switch having (a) a first flow electrode coupled to the source of the third supply voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to the third control signal for controlling current flow between the third switch'"'"'s flow electrodes, the circuit output signal making rising and falling circuit output transitions approximately between the first and third supply voltages, the circuit output signal staying approximately at the second supply voltage for a non-zero intermediate-level holding period during each circuit output transition, the transition time between the first and third supply voltages and/or between the second and third supply voltages being controlled.

5. (canceled)

11. (canceled)

14. (canceled)

17-18. -18. (canceled)

20-22. -22. (canceled)

23. An electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load, the circuit and conductor output signals respectively making corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level, inductance and capacitance of the conductor and the load producing resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition, the circuit including at least a first capacitor element between the intermediate voltage level and the first voltage level and at least a second capacitor element between the intermediate voltage level and the second voltage level.

26. A driver circuit according to claim 23, wherein a package lead inductance exists between the electrical conductor and a source of each of the pair of output voltage levels and wherein the first and second capacitor elements are such that a change in circuit output voltage causes return current flowing back into the driver to be split approximately equally between the package lead inductances.

27. A driver circuit according to claim 23, wherein the first and second capacitor elements provide decoupling capacitance between the output voltage levels.

24. (canceled)

25. A driver circuit according to claim 24 wherein the first and second capacitor elements form a split-reservoir capacitor.

28. An electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load, the circuit and conductor output signals respectively making corresponding circuit and conductor output transitions approximately between a first voltage, a second voltage and an intermediate voltage between the first and second voltages, the circuit comprising:

a first transistor having (a) a first flow electrode coupled to a source of the first voltage, (b) a second flow electrode coupled to an output node from which a circuit output signal is provided, and (c) a control electrode responsive to a first control signal for controlling current flow between the first transistor'"'"'s flow electrodes;

a second transistors having (a) a first flow electrode coupled to a source of the second voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a second control signal for controlling current flow between the second transistor'"'"'s flow electrodes;

a third transistors having (a) a first flow electrode coupled to a source of the intermediate voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a third control signal for controlling current flow between the third transistor'"'"'s flow electrodes; and

fourth and fifth transistors connected between the control electrode of the third transistor and the sources of the first and second voltage levels respectively, and control circuitry for selectively discharging the control electrode of the third transistor to the first and second voltage levels respectively through the fourth and fifth transistors such that the control electrode of the third transistor makes partial transitions between the first and second voltage levels,

whereby the output signal makes rising and falling circuit output transitions approximately between the first and second voltages controlled by the first, second and third control signals, and the circuit output signal stays approximately at the intermediate voltage for a non-zero intermediate-level holding period during each circuit output transition.

29. A driver circuit according to claim 28, further comprising control circuitry to provide the first, second and third control signals to cause the circuit output signal to stay approximately at the intermediate supply voltage for a non-zero intermediate-level holding period during each circuit output transition.

30-31. -31. (canceled)