Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal

• US 20070182470A1
• Filed: 08/02/2006
• Published: 08/09/2007
• Est. Priority Date: 08/03/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Heyne, Patrick
• Granted Patent: US 7,414,445 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.

Claims

1. A device for synchronizing an input clock signal with an output clock signal, comprising:

first variable, controllable delay means for generating a first clock signal and at least a second clock signal from a clock signal fed to the first delay means;

second delay means reproducing the characteristics of the delay of devices processing the output clock signal;

first phase comparing means for determining the phase between the input clock signal and a clock signal delayed by the second delay means;

first control means for controlling the delay of the second clock signal in the first delay means in correspondence with the phase determined by the the phase comparing means;

a bistable trigger circuit for controlling the edges of the clock signal fed to the first delay means;

second phase comparing means for determining the phase between the first clock signal delayed by means of the first delay means and the input clock signal; and

second control means for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparing means.

2. The device according to claim 1, wherein the input clock signal or a signal derived therefrom is guided to the set input, the first clock signal to the reset input of the bistable trigger circuit, and wherein the output signal thereof or a signal derived therefrom is guided to the first delay means as input signal.

3. The device according to claim 1, wherein the first delay means generates a third clock signal, and wherein, by means of a multiplexer, the second or the third clock signal of the first delay means is switched as input signal of the second delay means and simultaneously as output clock signal.

4. The device according to claim 3, wherein the second and the third clock signals are fed to a third phase comparing means, the output signal of which is fed to a third control means for controlling the delay of the second clock signal vis-à

-vis the third clock signal in the first delay means.

5. The device according to claim 1, the device further comprising an input device for adapting the signal level of the input clock signal.

6. The device according to claim 1, the device further comprising output means for adapting the level of the output clock signal to the devices following in the signal path of the output clock signal.

7. The device according to claim 1, wherein the first delay means is a tapped delay line with signal tappings for three pairs of clock signals.

8. The device according to claim 7, wherein the tapped delay line includes, for each pair of clock signals, a phase interpolator for generating a signal that lies between the phases of a clock signal pair with respect to time.

9. A method for synchronizing an input clock signal with an output clock signal, the method comprising:

deriving a first clock signal derived from the input clock signal;

deriving the output clock signal from the first clock signal derived from the input clock signal by delaying with a second controllable delay time by means of controllable delay means;

respective first edges of the first clock signal derived from the input clock signal are edges of the input clock signal which have been delayed in the delay means with a first variable, controllable delay time;

respective second edges of the first derived clock signal which are inverse edges to the first edges are triggered by the exiting of the first edges of the first derived clock signal from the delay means; and

determining the first delay time such that the respective second edges of the first derived clock signal coincide in time with every second edge of the input clock signal.

10. The method according to claim 9, wherein the input clock signal is fed to the one input of a bistable trigger circuit and the triggering of the respective second edges of the first derived clock signal is effected by that the first derived clock signal exiting from the delay means is fed to the other input of the bistable trigger circuit and that the output signal thereof is the input signal of the delay means.

11. The method according to claim 9, determining the delay of the first derived clock signal by a phase comparison between the input clock signal and the first derived clock signal exiting from the delay means.

12. The method according to claim 9, deriving a second and a third clock signal from the first derived clock signal by delaying with a second or third controllable delay time by means of the controllable delay means, wherein the second and third delay times differ by an integer multiple of a clock time;

and

switching the second or third clock signal as output clock signal by means of a multiplexer.

13. A device for synchronizing an input clock signal with an output clock signal, comprising:

a first variable, controllable delay for generating a first clock signal and at least a second clock signal from a clock signal fed to the first delay;

a second delay reproducing the characteristics of the delay of devices processing the output clock signal;

a first phase comparator for determining the phase between the input clock signal and a clock signal delayed by the second delay;

a first controller for controlling the delay of the second clock signal in the first delay in correspondence with the phase determined by the the phase comparator;

a bistable trigger circuit for controlling the edges of the clock signal fed to the first delay;

second phase comparator for determining the phase between the first clock signal delayed by means of the first delay means and the input clock signal; and

a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparing means.

14. The device according to claim 13, wherein the input clock signal or a signal derived therefrom is guided to the set input, the first clock signal to the reset input of the bistable trigger circuit, and wherein the output signal thereof or a signal derived therefrom is guided to the first delay means as input signal.

15. The device according to claim 13, wherein the first delay generates a third clock signal, and wherein, using a multiplexer, the second or the third clock signal of the first delay is switched as input signal of the second delay and simultaneously as output clock signal.

16. The device according to claim 15, wherein the second and the third clock signals are fed to a third phase comparator, the output signal of which is fed to a third controller for controlling the delay of the second clock signal vis-à

-vis the third clock signal in the first delay.

17. The device according to claim 16, the device further comprising an input device for adapting the signal level of the input clock signal.

18. The device according to claim 13, the device further comprising an output system for adapting the level of the output clock signal to the devices following in the signal path of the output clock signal.

19. The device according to claim 13, wherein the first delay is a tapped delay line with signal tappings for three pairs of clock signals.

20. The device according to claim 19, wherein the tapped delay line includes, for each pair of clock signals, a phase interpolator for generating a signal that lies between the phases of a clock signal pair with respect to time.

21. A device for synchronizing an input clock signal with an output clock signal, comprising:

first variable, controllable delay for generating a first clock signal and at least a second clock signal from a clock signal fed to the first delay;

a second delay;

a first phase comparator;

a first controller;

a bistable trigger circuit for controlling the edges of the clock signal fed to the first delay means;

a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal; and

a controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.