ISI reduction technique
First Claim
Patent Images
1. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:
- a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.
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Abstract
The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.
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Citations
17 Claims
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1. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:
a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect. - View Dependent Claims (2, 3)
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4. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:
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a voltage source, a first capacitor, a second capacitor, and at least one first switch configured to be switched in a way that for a first time period, a first voltage exists across both the first and the second capacitor, and for a third time period, a second voltage exists across both the first and the second capacitor; the circuit further comprising at least one pair of switches configured to be switched in a way that in a second time period between the first time period and the third time period, the first voltage existing across the second capacitor is reversed relative to the first voltage existing across the first capacitor, which causes the first capacitor to discharge through the second capacitor before being charged by the voltage source to the second voltage, thereby reducing the Inter-Symbol-Interference effect. - View Dependent Claims (5, 6)
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7. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:
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at least one voltage source, a first pair of capacitors comprising a first and a second capacitor and a second pair of capacitors comprising a third and a fourth capacitor and at least two pairs of switches configured to be switched in a way that, for a first time period, a first voltage exists across the first and the second capacitor being connected in parallel, and a second voltage exists across the third and the fourth capacitor being connected in parallel, wherein the second voltage has the same absolute value as the first voltage, but is opposite in sign; for a third time period, a third voltage exists across the first and the fourth capacitor, and a fourth voltage exists across the second and the third capacitor, wherein the fourth voltage has the same absolute value as the third voltage, but is opposite in sign; in a second time period between the first time period and the third time period, the first capacitor is disconnected from the second capacitor and connected to the fourth capacitor, which causes the first capacitor to discharge through the fourth capacitor before the first and the fourth capacitor are charged by the at least one voltage source to the third voltage, thereby reducing the Inter-Symbol-Interference effect, and the third capacitor is disconnected from the fourth capacitor and connected to the second capacitor, which causes the third capacitor to discharge through the second capacitor before the second and third capacitor are charged by the at least one voltage source to the fourth voltage, thereby reducing the Inter-Symbol-Interference effect. - View Dependent Claims (8, 9)
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- 10. A method for reducing an Inter-Symbol-Interference effect in a switch capacitor circuit having a voltage source, a first capacitor and a second capacitor, the method comprising the steps of charging the first capacitor to a first voltage by means of the voltage source, and discharging the first capacitor by means of the second capacitor.
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15. A method for reducing an Inter-Symbol-Interference effect in a switch capacitor comprising at least one voltage source, a first pair of capacitors comprising a first and a second capacitor and a second pair of capacitors comprising a third and a fourth capacitor and at least two pair of switches, the method comprising the steps of:
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charging the first and second capacitor to a first voltage by means of the at least one voltage source and charging the third and fourth capacitor to a second voltage by means of the at least one voltage source, wherein the second voltage has the same absolute value as the first voltage, but is opposite in sign; disconnecting the first capacitor from the second capacitor and connecting the first capacitor to the fourth capacitor, which causes the first capacitor to discharge through the fourth capacitor; disconnecting the third capacitor from the fourth capacitor and connecting the third capacitor to the second capacitor, which causes the third capacitor to discharge through the second capacitor. - View Dependent Claims (16, 17)
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Specification