Program method of flash memory capable of compensating read margin reduced due to charge loss

• US 20070183210A1
• Filed: 02/01/2007
• Published: 08/09/2007
• Est. Priority Date: 02/01/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Young-Ho, Choi, Ki-Hwan
• Granted Patent: US 7,489,558 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

Claims

1. A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states, the program method comprising:

programming selected memory cells with multi-bit data to have one of the plurality of states;

detecting programmed memory cells arranged within a predetermined threshold voltage region among the memory cells of the respective states, wherein the predetermined threshold region of the respective states is selected by both one of a first verify voltage and a read voltage and a second verify voltage, the second verify voltage being higher than the first verify voltage; and

programming the detected memory cells to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, wherein the second verify voltages are set to have different voltage levels.

2. The program method as recited in claim 1, wherein the plurality of states comprise:

a first state corresponding to an erased memory cell; and

a second, third and fourth states corresponding to a programmed memory cell.

3. The program method as recited in claim 2, wherein the detected memory cells have one of the second, third or fourth states.

4. The program method as recited in claim 2, wherein a voltage difference between said first and second verify voltages corresponding to the third state is greater than a voltage difference between said first and second verify voltages corresponding to the second state, and a voltage difference between said first and second verify voltages corresponding to the fourth state is greater than the voltage difference between said first and second verify voltages corresponding to the third state.

5. The program method as recited in claim 1, wherein the first verify voltage corresponding to a respective state is used to determine whether the selected memory cells are programmed with multi-bit data.

6. A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating at least one of first, second, third or fourth states, the program method comprising:

programming selected memory cells with multi-bit data to have one of the first, second, third or fourth states;

detecting programmed cells arranged within a predetermined threshold voltage region where programmed memory cells of the second state are distributed wherein the predetermined region of the second state is selected by both one of a first verify voltage and a read voltage and a second verify voltage associated with said second state, said second verify voltage associated with said second state being higher than said first verify voltage associated with said second state;

programming the detected memory cells to have a voltage equivalent to or higher than a second verify voltage corresponding to the second state;

detecting programmed memory cells arranged within a predetermined threshold voltage region where programmed memory cells of the third state are distributed, wherein the predetermined region of the third state is selected by both one of a first verify voltage and a read voltage and a second verify voltage associated with said third state, said second verify voltage associated with said third state being higher than said first verify voltage associated with said third state;

programming the detected memory cells to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to said third state;

detecting programmed memory cells arranged within a predetermined threshold voltage region where programmed memory cells of said fourth state are distributed, wherein the predetermined region of the fourth state is selected by both one of a first verify voltage and a read voltage and a second verify voltage associated with said fourth state, said second verify voltage associated with said fourth state being higher than said first verify voltage associated with said fourth state; and

programming the detected memory cells to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the fourth state, wherein voltage differences between first and second voltages associated with said second, and third states are different from each other.

7. The program method as recited in claim 6, wherein the second verify voltage associated with said third state is higher than the second verify voltage associated with said second state, and the second verify voltage associated with said fourth state is higher than the second verify voltage associated with said third state.

8. The program method as recited in claim 6, wherein the first verify voltages corresponding to the second, third and fourth states are used to determine whether the selected memory cells are programmed with multi-bit data.

9. The program method as recited in claim 6, wherein the first state indicates an erased memory cell, and each of said second, third and fourth states indicates a programmed memory cell.

10. A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating at least one of a plurality of states, the program method comprising:

programming selected memory cells with multi-bit data to have one of the plurality of states;

detecting programmed memory cells arranged within a predetermined threshold voltage region where programmed memory cells of at least two of the plurality of states are distributed wherein each predetermined region of the respective two or more states is selected by both one of a first verify voltage and a read voltage and a second verify voltage, the second verify voltage being higher than the first verify voltage; and

programming the programmed memory cells to have a threshold voltage equivalent to or higher than a second verify voltage corresponding to the at least two of the plurality of states, wherein second verify voltages corresponding to the at least two states of the plurality of states are set to have different voltage levels.

11. The program method as recited in claim 10, wherein the plurality of states comprise:

a first state indicating an erased memory cell;

a second state indicating a programmed memory cell;

a third state indicating a programmed memory cell; and

a fourth state indicating a programmed memory cell, said at least two of said plurality of states being said second and fourth states.

12. The program method as recited in claim 11, wherein the second verify voltage associated with the fourth state is higher than the second verify voltage associated with the third state.

13. The program method as recited in claim 10, wherein the plurality of states comprise:

a first state indicating an erased memory cell;

a second state indicating a programmed memory cell;

a third state indicating a programmed memory cell; and

a fourth state indicating a programmed memory cell, said at least two of said plurality of states being said second and third states.

14. The program method as recited in claim 13, wherein the second verify voltage associated with said third state is higher than the second verify voltage associated with the second state.