Optimal use of resources for signal processors

• US 20070183487A1
• Filed: 12/19/2006
• Published: 08/09/2007
• Est. Priority Date: 12/21/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Nemerix, SA
• Inventors: Genghi, Angelo
• Granted Patent: US 7,903,719 B2
• Time in Patent Office: Days
• US Class Current: 375/150
• CPC Class Codes: H04B 1/7077 Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
• CPC Class Codes: H04B 1/70775 Multi-dwell schemes, i.e. multiple accumulation times
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

Systems, methods and devices for signal processing are presented. In particular, methods for the detection of signals in CDMA-based systems are presented, together with corresponding devices. These methods provide more efficient use of correlation resources through proper identification of candidate signal peaks.

Claims

1. A signal processing method, comprising

receiving a signal;

performing a plurality of correlation steps over an entire code-frequency search space using a correlation engine having associated correlation resources to form a plurality of correlation results;

identifying from among the correlation results at least two candidates, each candidate comprising a code offset-frequency pair;

rejecting all candidates aside from the at least two candidates;

further correlating the at least two candidates;

identifying a candidate from the at least two candidates that represents a desired signal; and

wherein the step of further correlating the at least two candidates is conducted using fewer correlation resources than the step of performing a plurality of correlation steps.

2. The method of claim 1, wherein the step of identifying from among the correlation results at least two candidates comprises identifying at least N candidates, where N is a number greater than ten, and the step of further correlating the at least two candidates comprises further correlating the at least N candidates.

3. The method of claim 2, further comprising the steps of identifying a number less than N of intermediate candidates from the at least N candidates and further correlating the less than N intermediate candidates.

4. The method of claim 3, wherein the number N is at least one hundred.

5. The method of claim 2, wherein the step of identifying at least two candidates comprises comparing the at least two candidates against a threshold value that approximates a predetermined statistical probability that the candidate represents a desired signal.

6. The method of claim 5, wherein the desired signal has a power level less than or equal to −

145 dBmW.

7. A signal processing method, comprising:

receiving a first signal;

performing a pre-detection stage;

releasing a fraction of the correlation resources used in the pre-detection stage for the processing of a second signal; and

performing at least one distillation stage with the first signal.

8. The method of claim 7, wherein the step of performing at least one distillation stage comprises performing at least two distillation stages.

9. The method of claim 8, wherein at least one distillation stage is performed after every non-coherent integration interval after the pre-detection stage.

10. The method of claim 7, wherein the step of receiving a first signal comprises receiving a GNSS signal with a signal power of less than or equal to −

145 dBmW.

11. A signal processing receiver, comprising:

a correlation engine configured to correlate a known code against a received signal and comprising at least three channels;

a processor operatively connected to the correlation engine and in communication with a memory with executable instructions for carrying forward by at least two of the at least three channels a partial correlation performed by one of the at least three correlation channels; and

wherein the processor is further configured to release the one of the at least three correlation channels from correlation of the received signal when its partial correlation is complete.

12. The signal processing receiver of claim 11, wherein the correlation engine comprises at least one non-independent channel and at least two independent channels.

13. The signal processing receiver of claim 11,

wherein the at least three channels comprise a plurality of channel groups, each group having at least one channel member;

and

wherein the executable instructions include instructions for carrying forward from a previous channel group to a successive channel group a correlation partially performed by the previous group.

14. The signal processing receiver of claim 13, wherein each successive group is a smaller subset of the previous group.

15. The signal processing receiver of claim 13, comprising at least three channel groups.

16. An integrated circuit comprising,

a correlation engine, the correlation engine further comprising a plurality of channels;

the plurality of channels having at least two independent channels;

a subgroup of the plurality of channels being at least indirectly in communication, such that an acquisition search conducted by a channel can be further processed by at least two independent channels;

wherein each of the channels is configured to reject at least one corresponding candidate after an integration period; and

and wherein at least one channel is configured to be released after rejection of a plurality of candidates.

17. The integrated circuit of claim 16, wherein the subgroup of the plurality of channels being at least indirectly in communication are in communication via a digital signal processing core.

18. The integrated circuit of claim 16, wherein the at least two independent channels comprise at least ten independent channels, at least two of which are not configured for use as signal tracking channels.

19. The integrated circuit of claim 16, wherein the plurality of channels consists only of independent channels.

20. The integrated circuit of claim 16, wherein the plurality of channels comprises at least one massive-correlation channel.