Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board

• US 20070184604A1
• Filed: 03/23/2007
• Published: 08/09/2007
• Est. Priority Date: 10/05/1999
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Honda, Hirokazu
• Granted Patent: US 8,008,130 B2
• Time in Patent Office: Days
• US Class Current: 438/206
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/467 : Adding a circuit layer by thin film methods H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.

Claims

1. A method of forming an interconnection board, wherein during formation of said interconnection board, said interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than said interconnection board for suppressing said interconnection board from being bent.

2. The method as claimed in claim 1, wherein said interconnection board comprises a multilayer interconnection board having a multilevel interconnection structure.

3. The method as claimed in claim 1, further comprising the step of:

completely removing said high rigidity plate from said interconnection board, after said interconnection board is fabricated on said high rigidity plate.

4. The method as claimed in claim 3, wherein said high rigidity plate is made of a metal.

5. The method as claimed in claim 3, wherein said high rigidity plate is made of an alloy.

6. The method as claimed in claim 3, wherein said high rigidity plate is made of a ceramic.

7. The method as claimed in claim 3, wherein a base material of said interconnection board is an organic insulative material.

8. The method as claimed in claim 7, wherein said organic material is a polymer resin material.

9. The method as claimed in claim 1, further comprising the step of:

selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board, after said interconnection board is fabricated on said high rigidity plate.

10. The method as claimed in claim 9, further comprising the step of:

forming external electrodes on said plural generally column shaped electrically conductive layers so that said external electrodes are electrically connected through said plural generally column shaped electrically conductive layers to said interconnection board.

11. The method as claimed in claim 9, further comprising the step of:

forming an stress absorption layer being lower in rigidity than said plural generally column shaped electrically conductive layers, which fills gaps between said plural generally column shaped electrically conductive layers, so that said stress absorption layer surrounds said plural generally column shaped electrically conductive layers, whereby said stress absorption layer is in tightly contact with said plural generally column shaped electrically conductive layers.

12. The method as claimed in claim 11, further comprising the step of:

forming external electrodes on said plural generally column shaped electrically conductive layers so that said external electrodes are electrically connected through said plural generally column shaped electrically conductive layers to said interconnection board.

13. The method as claimed in claim 12, further comprising the step of:

forming a supporting plate having plural holes, into which said external electrodes are inserted, so that said supporting plate extends in parallel to said second surface of said buffer layer to form an inter-space between said supporting plate and said second surface of said buffer layer; and

forming a supporting sealing resin material which fills said inter-space and surrounding parts of said external electrodes so that said supporting sealing resin material is in tightly contact with said parts of said external electrodes for supporting said external electrodes.

14. The method as claimed in claim 1, further comprising the step of:

completely removing said high rigidity plate from said interconnection board, after said interconnection board is fabricated on said high rigidity plate;

forming a supporting plate having plural holes, into which said external electrodes are inserted, so that said supporting plate extends in parallel to said second surface of said buffer layer to form an inter-space between said supporting plate and said second surface of said buffer layer; and

forming a supporting sealing resin material which fills said inter-space and surrounding parts of said external electrodes so that said supporting sealing resin material is in tightly contact with said parts of said external electrodes for supporting said external electrodes.

15. The method as claimed in claim 1, further comprising the step of:

completely removing said high rigidity plate from said interconnection board, after said interconnection board is fabricated on said high rigidity plate;

bonding plural generally column shaped electrically conductive layers to said interconnection board via an adhesive; and

forming external electrodes on said plural generally column shaped electrically conductive layers so that said external electrodes are electrically connected through said plural generally column shaped electrically conductive layers to said interconnection board.

16. The method as claimed in claim 15, further comprising the step of:

forming a supporting plate having plural holes, into which said plural generally column shaped electrically conductive layers with said external electrodes are inserted, and said supporting plate extending in parallel to said second surface of said interconnection board to form an inter-space between said supporting plate and said second surface of said interconnection board; and

forming a supporting sealing resin material which fills said inter-space and surrounds both said plural generally column shaped electrically conductive layers and parts of said external electrodes so that said supporting sealing resin material is in tightly contact with said plural generally column shaped electrically conductive layers and said parts of said external electrodes for supporting said external electrodes.

17. The method as claimed in claim 1, further comprising the step of:

mounting at least a semiconductor chip on said interconnection board; and

completely removing said high rigidity plate from said interconnection board.

18. The method as claimed in claim 1 further comprising the step of:

mounting at least a semiconductor chip on said interconnection board;

forming at least a heat spreader on said at least semiconductor chip; and

completely removing said high rigidity plate from said interconnection board.

19. The method as claimed in claim 1 further comprising the step of:

mounting at least a semiconductor chip on said interconnection board; and

selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board.

20. The method as claimed in claim 1 further comprising the step of:

mounting at least a semiconductor chip on said interconnection board;

forming at least a heat spreader on said at least semiconductor chip; and

selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board.