Opto-thermal annealing mask and method

• US 20070187670A1
• Filed: 02/16/2006
• Published: 08/16/2007
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Sung, Chun-Yung, Narayan, Chandrasekhar, Hsu, Louis, Mandelman, Jack
• Granted Patent: US 7,804,148 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.

Claims

1. A structure comprising:

a thermal dissipative layer located over a substrate;

a reflective layer located aligned upon the thermal dissipative layer; and

a transparent capping layer located aligned upon the reflective layer.

2. The structure of claim 1 wherein the transparent capping layer has a thickness from about 10 to about 100 angstroms.

3. The structure of claim 1 wherein the substrate comprises a bulk semiconductor substrate.

4. The structure of claim 1 wherein the substrate comprises a semiconductor-on-insulator substrate.

5. The structure of claim 1 wherein the substrate comprises a hybrid semiconductor substrate comprising at least one bulk semiconductor region and at least one semiconductor-on-insulator region.

6. The structure of claim 1 wherein:

the thermal dissipative layer comprises a refractory metal; and

the reflective layer comprises a non-refractory metal.

7. The structure of claim 1 wherein:

the thermal dissipative layer comprises a thermal dissipative diamond like carbon material; and

the reflective layer comprises a non-refractory metal.

8. The structure of claim 1 further comprising an optical interference layer located laterally with respect to the thermal dissipative layer over the substrate.

19. The field effect transistor of claim 1 wherein the transparent capping layer has a thickness from about 10 to about 100 angstroms.

20. The field effect transistor of claim 19 wherein:

the thermal dissipative layer comprises a refractory metal; and

the reflective layer comprises a non-refractory metal.

9. A structure comprising:

a semiconductor substrate including a plurality of separate lateral surface semiconductor regions each having a separate thermal annealing budget;

an opto-thermal annealing mask stack layer located registered with respect to a second lateral surface semiconductor region having a second thermal annealing budget and leaving uncovered a separate first lateral surface semiconductor region having a first thermal annealing budget greater than the second thermal annealing budget, the opto-thermal annealing mask stack layer comprising;

a thermal dissipative layer located over the semiconductor substrate;

a reflective layer located aligned upon the thermal dissipative layer; and

a transparent capping layer located aligned upon the reflective layer.

10. The structure of claim 9 further comprising an opto-thermal annealing interference mask layer located registered with respect to a third lateral surface semiconductor region separate from the first lateral surface semiconductor region and the second lateral surface semiconductor region, the third lateral surface semiconductor region having a third thermal annealing budget between the first thermal annealing budget and the second thermal annealing budget.

11. The structure of claim 10 wherein the semiconductor substrate comprises a hybrid semiconductor substrate comprising:

a bulk semiconductor region comprising the first lateral surface semiconductor region;

a first semiconductor-on-insulator region having a comparatively thin semiconductor surface layer comprising the second lateral surface semiconductor region; and

a second semiconductor-on-insulator region having a comparatively thick semiconductor surface layer comprising the third lateral surface semiconductor region.

12. The structure of claim 9 wherein:

the thermal dissipative layer comprises a refractory metal; and

the reflective layer comprises a non-refractory metal.

13. The structure of claim 9 wherein:

the thermal dissipative layer comprises a thermal dissipative diamond like carbon material; and

the reflective layer comprises a non-refractory metal.

15. The method of claim 13 wherein the opto-thermally annealing utilizes a laser opto-thermal radiation source.

16. The method of claim 13 further comprising forming an opto-thermal annealing interference mask layer over a third lateral surface semiconductor region of the semiconductor substrate separate from the first lateral surface semiconductor region and the second lateral surface semiconductor region, prior to opto-thermally annealing the masked semiconductor substrate while using the opto-thermal radiation source.

17. The method of claim 16 wherein the forming comprises:

utilizing a hybrid semiconductor substrate comprising;

a bulk semiconductor region comprising the first lateral surface semiconductor region;

a first semiconductor-on-insulator region having a comparatively thin semiconductor surface layer comprising the second lateral surface semiconductor region; and

a second semiconductor-on-insulator region having a comparatively thick semiconductor surface layer comprising the third lateral surface semiconductor region.

14. A method for opto-thermally annealing a semiconductor substrate comprising:

forming an opto-thermal annealing mask stack layer over a second lateral surface semiconductor region of a semiconductor substrate, while leaving uncovered a first lateral surface semiconductor region of the semiconductor substrate separate from the second lateral surface semiconductor region, the opto-thermal annealing mask stack layer comprising an aligned tri-layer laminate including, in outward progression from the semiconductor substrate;

a thermal dissipative layer;

a reflective layer; and

a transparent capping layer, and

opto-thermally annealing the masked semiconductor substrate while using an opto-thermal radiation source.

18. A field effect transistor comprising:

a semiconductor substrate including a pair of source/drain regions that is separated by a channel region; and

a gate electrode located over the channel region, where the gate electrode comprises;

a thermal dissipative layer;

a reflective layer located aligned upon the thermal dissipative layer; and

a transparent capping layer located aligned upon the reflective layer.