Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same

• US 20070187775A1
• Filed: 02/07/2007
• Published: 08/16/2007
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Okhonin, Serguei, Carman, Eric, Jones, Mark-Eric
• Granted Patent: US 7,542,345 B2
• Time in Patent Office: Days
• US Class Current: 257/370
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors

Abstract

There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).

Claims

1. An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes;

a source region;

a drain region;

a body region disposed between the source region and the drain region,

wherein the body region is electrically floating; and

a gate disposed over the body region;

wherein each memory cell includes;

(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;

(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; and

(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor; and

data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein, (ii) second write control signals to the memory cell to write the second data state therein, and (iii) third write control signals to the memory cell to write the third data state therein.

2. An integrated circuit device of claim 1 wherein, in response to:

the first write control signals applied to the memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor, and

the second write control signals applied to the memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor.

3. The integrated circuit device of claim 1 wherein the first write control signals include:

(1) a first temporally changing signal applied to the gate, and

(2a) a second temporally changing signal applied to the source region, or (2b) a second temporally changing signal applied to the drain region.

4. The integrated circuit device of claim 1 wherein:

the first write control signals include a first temporally changing signal applied to the source region;

the second write control signals include a second temporally changing signal applied to the source region; and

the third write control signals include a third temporally changing signal applied to the source region.

5. The integrated circuit device of claim 4 wherein:

the first temporally changing signal includes a first voltage having a first amplitude and a second voltage having a second amplitude; and

the second temporally changing signal includes the first voltage having the first amplitude and a third voltage having a third amplitude; and

the third temporally changing signal includes the first voltage having the first amplitude and a fourth voltage having a fourth amplitude.

6. The integrated circuit device of claim 1 wherein:

the first write control signals include a first temporally changing signal applied to the drain region;

the second write control signals include a second temporally changing signal applied to the drain region; and

the third write control signals include a third temporally changing signal applied to the drain region.

7. The integrated circuit device of claim 6 wherein:

the first temporally changing signal includes a first voltage having a first amplitude and a second voltage having a second amplitude; and

the second temporally changing signal includes the first voltage having the first amplitude and a third voltage having a third amplitude; and

the third temporally changing signal includes the first voltage having the first amplitude and a fourth voltage having a fourth amplitude.

8. The integrated circuit device of claim 1 wherein the signal applied to the gate temporally changes relative to the signal applied to the drain region to cause, provide, produce and/or induce the majority carriers to accumulate in a portion of the electrically floating body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the electrically floating body region.

9. The integrated circuit device of claim 8 wherein the signal applied to the gate changes or terminates before the signal applied to the drain region.

11. The integrated circuit device of claim 1 further including:

data sense circuitry, coupled to the memory cell, to sense the data state of the memory cell; and

wherein, in response to read control signals applied to the memory cell, the electrically floating body transistor generates a read bipolar transistor current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the read bipolar transistor current.

12. The integrated circuit device of claim 11 wherein the read control signals include a signal applied to the gate, source region, and drain region to cause, force and/or induce the read bipolar transistor current which is representative of the data state of the memory cell and wherein the signal applied to the source region includes a positive voltage pulse.

13. The integrated circuit device of claim 11 wherein the read control signals include a signal applied to the gate, source region, and drain region to cause, force and/or induce the read bipolar transistor current which is representative of the data state of the memory cell and wherein the signal applied to the gate includes a negative voltage pulse.

14. An integrated circuit device comprising:

a memory cell array including a;

plurality of word lines;

plurality of source lines;

plurality of bit lines; and

plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes;

a source region coupled to an associated source line;

a drain region coupled to an associated bit line;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating;

a gate disposed over the body region and coupled to an associated word line; and

wherein each memory cell includes more than three data states, including;

(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;

(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;

(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor; and

(iv) a fourth data state which is representative of a fourth charge in the body region of the electrically floating body transistor; and

data write circuitry, coupled to each of the memory cells, to apply (i) first write control signals to the memory cells to write the first data state therein, (ii) second write control signals to the memory cells to write the second data state therein, (iii) third write control signals to the memory cells to write the third data state therein and (iv) fourth write control signals to the memory cells to write the fourth data state therein.

15. An integrated circuit device of claim 14 wherein, in response to:

the first write control signals applied to a predetermined memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor,

the second write control signals applied to the predetermined memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor, and

the third write control signals applied to the predetermined memory cell, the electrically floating body transistor thereof generates a third bipolar transistor current which substantially provides the third charge in the body region of the electrically floating body transistor.

16. An integrated circuit device comprising:

a memory cell array including a;

plurality of word lines;

plurality of source lines;

plurality of bit lines; and

plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes;

a source region coupled to an associated source line;

a drain region coupled to an associated bit line;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating;

a gate disposed over the body region and coupled to an associated word line; and

wherein each memory cell includes more than two data states, including;

(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor;

(iii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; and

(iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor; and

data sense circuitry, coupled to the plurality of memory cells, to sense the data state of the plurality of memory cells; and

wherein, in response to read control signals applied to the plurality of memory cells, the electrically floating body transistor of each memory cell generates a read bipolar transistor current which is representative of the data state of the associated memory cell and wherein the data sense circuitry determines the data state of the associated memory cell at least substantially based on the read bipolar transistor current.

17. The integrated circuit device of claim 16 wherein the read control signals include a signal applied to the gate, source region, and drain region of a transistor of a predetermined memory cell to cause, force and/or induce the read bipolar transistor current which is representative of the data state of the predetermined memory cell and wherein the signal applied to the gate of the associated transistor includes a positive voltage pulse.

18. The integrated circuit device of claim 16 wherein the read control signals include a signal applied to the gate, source region, and drain region of a transistor of a predetermined memory cell to cause, force and/or induce the read bipolar transistor current which is representative of the data state of the predetermined memory cell and wherein the signal applied to the gate of the associated transistor includes a negative voltage pulse.

19. An integrated circuit device of claim 16 further including data write circuitry, coupled to each of the memory cells, to apply (i) first write control signals to a predetermined memory cell to write the first data state therein, (ii) second write control signals to the predetermined memory cell to write the second data state therein, and (iii) third write control signals to the predetermined memory cell to write the third data state therein.

20. An integrated circuit device of claim 19 wherein, in response to:

the first write control signals applied to the predetermined memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor, and

the second write control signals applied to the predetermined memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor.