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Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same

  • US 20070188242A1
  • Filed: 07/14/2006
  • Published: 08/16/2007
  • Est. Priority Date: 02/15/2006
  • Status: Active Grant
First Claim
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1. A Phase Locked Loop (PLL), comprising:

  • a Phase Frequency Detector (PFD) for comparing a phase or frequency of a reference signal with a phase or frequency of an output signal and outputting an up signal or a down signal based on a comparison result;

    a charge pump circuit for generating a pumping current in response to the up signal or the down signal and increasing or decreasing the pumping current in response to a detection signal;

    a loop filter for outputting control voltage according to the pumping current;

    a Voltage Controlled Oscillator (VCO) for outputting the output signal having a frequency determined based on the control voltage; and

    a peak voltage detector for detecting a peak value of the control voltage and outputting the detection signal based on a detection result.

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