Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same

• US 20070188242A1
• Filed: 07/14/2006
• Published: 08/16/2007
• Est. Priority Date: 02/15/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Song, Keun
• Granted Patent: US 7,443,249 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase locked loop for stably operating in a matter that is insensitive to variation in PVT and a method of operating the same. The PLL according to the present invention includes a PFD, a charge pump circuit, a loop filter, a VCO, and a peak voltage detector. The PFD compares a phase or frequency of a reference signal with a phase or frequency of an output signal and outputs an up signal or a down signal based on the comparison result. The charge pump circuit generates a pumping current in response to the up signal or the down signal and increases or decreases the pumping current in response to a detection signal. The loop filter outputs control voltage according to the pumping current. The VCO outputs the output signal having a frequency determined based on the control voltage. The peak voltage detector detects the peak value of the control voltage and outputs the detection signal based on the detection result. The PLL detects the peak value of control voltage and controls the operation of a charge pump circuit based on the detection result thereby decreasing the peaking and ringing phenomena of the control voltage and then stably operating in a manner that is insensitive to variation in PVT.

Claims

1. A Phase Locked Loop (PLL), comprising:

a Phase Frequency Detector (PFD) for comparing a phase or frequency of a reference signal with a phase or frequency of an output signal and outputting an up signal or a down signal based on a comparison result;

a charge pump circuit for generating a pumping current in response to the up signal or the down signal and increasing or decreasing the pumping current in response to a detection signal;

a loop filter for outputting control voltage according to the pumping current;

a Voltage Controlled Oscillator (VCO) for outputting the output signal having a frequency determined based on the control voltage; and

a peak voltage detector for detecting a peak value of the control voltage and outputting the detection signal based on a detection result.

2. The PLL set forth in claim 1, wherein the charge pump circuit comprises:

a first charge pump for generating a first current in response to the up signal or the down signal;

a second charge pump for generating a second current in response to the up signal or the down signal; and

a switching circuit connected in parallel to the first charge pump at an output node for connecting or disconnecting an output terminal of the second charge pump to or from the output node.

3. The PLL set forth in claim 2, wherein the first charge pump comprises:

a first switch connected between internal voltage and the output node for being turning on or off in response to the up signal; and

a second switch connected between the output node and ground voltage for being turning on or off in response to the down signal,

wherein, when any one of the first and second switches, the remaining switch is turned off, and when the first switch is turned on, the first current is supplied to the output node.

4. The PLL set forth in claim 2, wherein the second charge pump comprises:

a first switch connected between internal voltage and an internal output node for being turning on or off in response to the up signal; and

a second switch connected between the internal output node and ground voltage for being turning on or off in response to the down signal,

wherein, when any one of the first and second switches, the remaining switch is turned off, and when the first switch is turned on, the second current is supplied to the switching circuit.

5. The PLL set forth in claim 4, wherein the switching circuit comprises:

an inverter for inverting the detection signal and outputting the inverted detection signal;

a third switch connected between the internal output node and the output node for being turned on or off in response to the detection signal and the inverted detection signal.

6. The PLL set forth in claim 2, wherein, when the switching circuit connects the output terminal of the second charge pump to the output node, an amount of the pumping current is determined based on a sum of the first and second currents, and when the switching circuit disconnects the output terminal of the second charge pump from the output node, the amount of the pumping current is determined based on the first current.

7. The PLL set forth in claim 1, wherein the peak voltage detector enables the detection signal when the control voltage becomes higher than a predetermined value, and, when the detection signal is enabled, the switching circuit disconnects the output terminal of the second charge pump from the output node in response to the detection signal.

8. The PLL set forth in claim 1, wherein the peak voltage detector comprises:

a voltage dividing circuit for dividing the control voltage and outputting a divided voltage;

a bias voltage generator for generating a bias voltage in response to the divided voltage;

an internal output circuit for outputting an internal detection signal in response to the bias voltage; and

an output logic circuit for outputting the detection signal in response to a power-up signal or the internal detection signal.

9. The PLL set forth in claim 8, wherein the voltage dividing circuit increases the divided voltage when the control voltage increases, and decreases the bias voltage when the divided voltage increases.

10. The PLL set forth in claim 8, wherein the voltage dividing circuit comprises:

a first resistor connected between the control voltage and the output node; and

a second resistor connected between the output node and ground voltage,

wherein the divided voltage is determined based on a ratio of the first and second resistors and the control voltage.

11. The PLL set forth in claim 8, wherein the bias voltage generator comprises:

a pull-up transistor for supplying the internal voltage to the output node; and

a pull-down transistor connected to the ground voltage at the output node for being turned on or off in response to the divided voltage,

wherein, when the pull-down transistor is turned on, the bias voltage generated at the output node decreases, and, when the pull-down transistor is turned off, the bias voltage increases.

12. The PLL set forth in claim 8, wherein the internal output circuit comprises:

a pull-up transistor connected between the internal voltage and the output node for being turned on or off in response to the bias voltage; and

a pull-down transistor connected between the output node and the ground voltage for being turned on or off in response to the bias voltage,

wherein, when any one of the pull-up and pull-down transistors is turned on, the remaining transistor is turned off, and when any one of the pull-up and pull-down transistors is turned on, the internal detection signal output to the output node is enabled or disabled.

13. The PLL set forth in claim 8, wherein the output logic circuit comprises an AND gate for outputting the detection signal in response to the power-up signal and the internal detection signal.

14. A Phase Locked Loop (PLL), comprising:

a PFD for comparing a phase or frequency of a reference signal with a phase or frequency of a divided signal and outputting an up signal or a down signal based on a comparison result;

a charge pump circuit for generating a pumping current in response to the up signal or the down signal and increasing or decreasing the pumping current in response to a detection signal;

a loop filter for outputting control voltage according to the pumping current;

a VCO for outputting the output signal having a frequency determined based on the control voltage;

a divider for dividing the output signal in a predetermined division ratio and outputting the divided signal; and

a peak voltage detector for detecting a peak value of the control voltage and outputting the detection signal based on a detection result.

15. The PLL set forth in claim 14, wherein the charge pump circuit comprises:

a first charge pump for generating a first current in response to the up signal or the down signal;

a second charge pump for generating a second current in response to the up signal or the down signal; and

a switching circuit connected in parallel to the first charge pump at an output node for connecting or disconnecting an output terminal of the second charge pump to or from the output node.

16. The PLL set forth in claim 15, wherein the first charge pump comprises:

a first switch connected between internal voltage and the output node for being turning on or off in response to the up signal; and

a second switch connected between the output node and ground voltage for being turning on or off in response to the down signal,

wherein, when any one of the first and second switches, the remaining switch is turned off, and when the first switch is turned on, the first current is supplied to the output node.

17. The PLL set forth in claim 15, wherein the second charge pump comprises:

a first switch connected between internal voltage and an internal output node for being turning on or off in response to the up signal; and

a second switch connected between the internal output node and ground voltage for being turning on or off in response to the down signal,

wherein, when any one of the first and second switches, the remaining switch is turned off, and when the first switch is turned on, the second current is supplied to the switching circuit.

18. The PLL set forth in claim 17, wherein the switching circuit comprises:

an inverter for inverting the detection signal and outputting the inverted detection signal;

a third switch connected between the internal output node and the output node for being turned on or off in response to the detection signal and the inverted detection signal.

19. The PLL set forth in claim 14, wherein the peak voltage detector enables the detection signal when the control voltage becomes higher than a predetermined value, and, when the detection signal is enabled, the switching circuit disconnects the output terminal of the second charge pump from the output node in response to the detection signal.

20. The PLL set forth in claim 14, wherein the peak voltage detector comprises:

a voltage dividing circuit for dividing the control voltage and outputting a divided voltage;

a bias voltage generator for generating a bias voltage in response to the divided voltage;

an internal output circuit for outputting an internal detection signal in response to the bias voltage; and

an output logic circuit for outputting the detection signal in response to a power-up signal or the internal detection signal.

21. The PLL set forth in claim 20, wherein the voltage dividing circuit increases the divided voltage when the control voltage increases, and decreases the bias voltage when the divided voltage increases.

22. The PLL set forth in claim 20, wherein the voltage dividing circuit comprises:

a first resistor connected between the control voltage and the output node; and

a second resistor connected between the output node and ground voltage,

wherein the divided voltage is determined based on a ratio of the first and second resistors and the control voltage.

23. The PLL set forth in claim 20, wherein the bias voltage generator comprises:

a pull-up transistor for supplying the internal voltage to the output node; and

a pull-down transistor connected to the ground voltage at the output node for being turned on or off in response to the divided voltage,

wherein, when the pull-down transistor is turned on, the bias voltage generated at the output node decreases, and, when the pull-down transistor is turned off, the bias voltage increases.

24. The PLL set forth in claim 20, wherein the internal output circuit comprises:

a pull-up transistor connected between the internal voltage and the output node for being turned on or off in response to the bias voltage; and

a pull-down transistor connected between the output node and the ground voltage for being turned on or off in response to the bias voltage,

wherein, when any one of the pull-up and pull-down transistors is turned on, the remaining transistor is turned off, and when any one of the pull-up and pull-down transistors is turned on, the internal detection signal output to the output node is enabled or disabled.

25. The PLL set forth in claim 20, wherein the output logic circuit comprises an AND gate for outputting the detection signal in response to the power-up signal and the internal detection signal.

26. The PLL set forth in claim 15, wherein, when the switching circuit connects the output terminal of the second charge pump to the output node, an amount of the pumping current is determined based on a sum of the first and second currents, and when the switching circuit disconnects the output terminal of the second charge pump from the output node, the amount of the pumping current is determined based on the first current.

27. A method of operating a PLL for generating an output signal in synchronous with a reference signal, comprising:

comparing a phase or frequency of a reference signal with a phase or frequency of an output signal and outputting an up signal or a down signal based on a comparison result;

generating a pumping current in response to the up signal or the down signal and increasing or decreasing the pumping current in response to a detection signal;

outputting control voltage according to the pumping current;

adjusting the frequency of the output signal according to the control voltage;

detecting a peak value of the control voltage and outputting the detection signal based on a detection result; and

adjusting an amount of the pumping current in response to the detection signal.

28. The PLL set forth in claim 27, wherein the outputting the detection signal comprises:

dividing the control voltage and outputting a divided voltage;

generating a bias voltage in response to the divided voltage;

outputting an internal detection signal in response to the bias voltage; and

outputting the detection signal in response to a power-up signal and the internal detection signal.

29. The PLL set forth in claim 27, wherein the adjusting the amount of the pumping current comprises:

the detection signal increasing the amount of the pumping current by operating both first and second charge pumps when the peak value of the control voltage is lower than a predetermined value; and

the detection signal decreasing the amount of the pumping current by operating any one of the first and second charge pumps when the peak value of the control voltage is higher than a predetermined value.