Array substrate of liquid crystal display and fabricating method thereof

• US 20070188671A1
• Filed: 04/16/2007
• Published: 08/16/2007
• Est. Priority Date: 07/07/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Se, Kim, Woo, Hwang, Kwang
• Granted Patent: US 7,522,224 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13629 Multilayer wirings

Abstract

An array substrate of a liquid crystal device has a plurality of gate lines, data lines, pixel areas, and thin film transistors, wherein the gate lines are formed from a material of a first and second metal layer, and wherein the first metal layer of the gate line is extended on the pixel area. Also, a display device has first and second gate lines and a data line on a substrate, a thin film transistor, a pixel electrode, a first storage electrodes extending from the second gate line and wherein at least one of the first and second gate lines and the data line includes first and second line layers respectively formed of an oxidized metal later and a metal layer.

Claims

1. An array substrate of a liquid crystal display, comprising:

a substrate;

a plurality of gate lines formed on the substrate;

a plurality of data lines formed on the substrate to intersect perpendicularly to the gate lines;

pixel areas defined by the gate lines and the data lines;

thin film transistors each formed at each intersection of the gate line and the data line; and

pixel electrodes each formed on each pixel area to be connected to the thin film transistor,

wherein the gate lines are formed from a disposed material of a first and second metal layer, and wherein the first metal layer of the gate line is extended on the pixel area.

2. The array substrate according to claim 1, wherein the first metal layer of the gate line is an oxidized metal layer.

3. The array substrate according to claim 1, wherein the first metal layer of the gate line is formed from any one of a titanium oxide and an indium zinc oxide.

4. The array substrate according to claim 1, wherein the first metal layer of the gate line is below 50 Å

in the thickness.

5. The array substrate according to claim 1, wherein the second metal layer of the gate line is formed from any one of a copper and an aluminum.

6. The array substrate according to claim 1, wherein the first metal layer of the gate line extended on the pixel area forms a first electrode of a storage capacitor.

7. The array substrate according to claim 1, wherein the thin film transistor includes:

a gate electrode connected to the gate line;

an active layer formed on a gate insulating film over the gate electrode;

a source electrode formed on the active layer and connected to the data line; and

a drain electrode formed on the active layer with a constant distance from the source electrode and connected to the pixel electrode,

wherein the data line, the source electrode and the drain electrode are formed from a disposed material of a third metal layer and a fourth metal layer.

8. The array substrate according to claim 7, wherein the third metal layer is an oxidized metal layer.

9. The array substrate according to claim 7, wherein the third metal layer is any one of a titanium oxide and an indium zinc oxide.

10. The array substrate according to claim 7, wherein the third metal layer is below 50 Å

in the thickness.

11. The array substrate according to claim 7, wherein the third metal layer has a extending part on the pixel, the extending part overlapping the extending part of the first metal layer with the gate insulating film therebetween and forming a second electrode of the storage capacitor.

12. The array substrate according to claim 11, further comprises an insulating film between the second electrode of the storage capacitor and the pixel electrode,

wherein the second electrode of the storage capacitor are electrically connected to the pixel electrode through a contact hole formed in the insulating film over the gate line.

13. The array substrate according to claim 11, wherein the storage capacitor formed by the extending parts of the first and third metal layers has the capacitance of above 100 times in opposition to a parasitic capacitor between the gate electrode and the source electrode of the thin film transistor.

14. An array substrate of a display device, comprising:

a gate line having first and second gate line layers formed respectively of a first oxidized metal layer and a first metal layer on a substrate;

a first storage electrode extending from the gate line;

a second storage electrode over the gate line and the first storage electrode;

a TFT (thin film transistor) and a data line on the substrate; and

a pixel electrode in electrical contact with the second storage electrode.

15. The array substrate according to claim 14, wherein the data line includes first and second data line layers respectively formed of a second oxidized metal layer and a second metal layer.

16. The array substrate according to claim 14, wherein the TFT includes:

a gate electrode extending from another gate line adjacent to the gate line having the first and second gate line layers;

a source electrode extending from the data line; and

a drain electrode in electrical contact with the pixel electrode.

17. The array substrate according to claim 16, wherein the gate electrode includes first and second gate electrode layers respectively formed of the first oxidized metal layer and the first metal layer.

18. The array substrate according to claim 16, wherein at least one of the source and drain electrodes includes first and second electrode layers respectively formed of a second oxidized metal layer and a second metal layer.

19. A display device comprising:

first and second gate lines and a data line on a substrate, the first and second gate lines crossing the data line;

a TFT (thin film transistor) at an intersection area of the first gate line and the data line;

a pixel electrode connected to the TFT; and

a first storage electrode extending from the second gate line,

wherein at least one of the first and second gate lines and the data line includes first and second line layers respectively formed of an oxidized metal layer and a metal layer.

20. The display device according to claim 19, wherein the TFT includes:

a gate electrode extending from the first gate line;

a source electrode extending from the data line; and

a drain electrode in contact with the pixel electrode,

wherein at least one of the gate, source and drain electrodes includes first and second electrode layers respectively formed of an oxidized metal layer and a metal layer.

21. The display device according to claim 19, further comprising:

a second storage electrode over the second gate line and the first storage electrode, and in contact with the pixel electrode.