Silicon-on-insulator near infrared active pixel sensor array

• US 20070190681A1
• Filed: 02/13/2006
• Published: 08/16/2007
• Est. Priority Date: 02/13/2006
• Status: Abandoned Application

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maa, Jer-Shen, Lee, Jong-Jan, Hsu, Sheng, Tweet, Douglas
• Application Number:
  US11/352,724
• Publication Number:
  US 20070190681A1
• Time in Patent Office: Days
• US Class Current: 438/54
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14649 Infrared imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×10¹⁶ to about 5×10¹⁸ cm⁻³.

Claims

1. A method for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate, the method comprising:

forming a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer;

forming a second wafer comprising a first silicon oxide layer and a second Si layer;

bonding the first wafer to the second wafer, forming a SOI substrate;

forming a diode with a p-n junction space charge region extending into the first Si substrate;

forming a thin-film transistor (TFT) in the second Si layer; and

,

forming interconnects between the TFT and the diode.

2. The method of claim 1 wherein forming the first wafer includes:

providing the high resistivity first Si substrate;

doping the first Si substrate; and

,

in response to the doping, forming the first Si layer overlying the first Si substrate.

3. The method of claim 2 wherein forming the first Si layer includes forming the first Si layer with a dopant concentration in the range of about 1×

10¹⁶ to about 5×

10¹⁸ cm<sup>−

3</sup>.

4. The method of claim 2 wherein forming the first Si layer includes forming the first Si layer with a thickness in the range of about 50 to 300 nanometers (nm).

5. The method of claim 2 wherein forming the first wafer includes forming a second silicon oxide layer overlying the first Si substrate prior to doping the first Si substrate;

and,

wherein bonding the first wafer to the second wafer includes bonding the second silicon oxide layer of the first wafer to the first silicon oxide layer of the second wafer.

6. The method of claim 1 wherein forming the second wafer includes:

providing a second Si substrate;

oxidizing a surface of the second Si substrate, forming the first silicon oxide layer;

implanting ions into the second Si substrate;

creating a defect plane in the second Si substrate; and

,

splitting the bonded first and second wafers along the defect plane.

7. The method of claim 6 wherein providing the second Si substrate includes providing a second Si substrate selected from the group consisting of undoped, lightly doped, and moderately doped Si.

8. The method of claim 6 wherein implanting ions into the second Si substrate includes:

implanting ions selected from the group consisting of H₂+, H+, Ar+, He+, and Ne+; and

,

implanting ions with a dosing density in the range of about 5×

10¹⁵ to about 5×

10¹⁶ cm<sup>−

2</sup>.

9. The method of claim 6 wherein creating the defect plane includes creating the defect plane about 0.1 to 1 micrometers below the first silicon oxide interface to the second Si substrate.

10. The method of claim 6 wherein splitting the bonded first and second wafers includes annealing at a temperature in the range of about 350 to 800°

C.; and

,

the method further comprising;

performing a chemical-mechanical polish (CMP) process along the exposed defect plane in the second Si substrate;

in response to the CMP, creating the second Si layer thickness in the range of about 20 to 500 nm.

11. The method of claim 1 wherein the first Si substrate has a resistivity of greater than about 100 ohm-cm.

12. The method of claim 1 wherein forming the SOI substrate includes forming the first silicon oxide layer with a first sidewall and an opposing second sidewall;

wherein forming the diode includes;

forming a first heavily doped region in the first Si layer adjacent the silicon oxide layer first sidewall;

forming a second heavily doped region, opposite in polarity to the first heavily doped region, in the first Si layer adjacent the silicon oxide layer second sidewall;

forming a first space charge region between the first and second heavily doped regions, extending into the first Si substrate at a depth greater than about 2 micrometers, in response to a reverse bias voltage of about 2 volts.

13. The method of claim 12 wherein forming the diode includes forming a second space charge region extending through the first Si layer at a depth less than the first Si layer thickness, without intersecting the interface between the first Si layer and the first silicon oxide layer, in response to a reverse bias of about 5 volts.

14. The method of claim 1 wherein forming the first wafer includes forming a p-type doped first Si layer and a p-type doped high resistance first Si substrate;

and,

wherein forming the diode includes forming an n+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup> and a p+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, in the first Si layer.

15. The method of claim 14 wherein forming the diode includes forming an n-region adjacent the n+ region, separating the n+region from the p+ region, with a dopant concentration greater than the first Si layer dopant concentration, in the range of about 2×

10¹⁶ cm<sup>−

3</sup> to 1×

10¹⁹ cm<sup>−

3</sup>.

16. The method of claim 15 wherein forming the p+ region includes forming a p+ perimeter in the first Si layer surrounding the n+ and n regions.

17. The method of claim 1 wherein forming the first wafer includes forming a p-type doped first Si layer and an n-type doped high resistance first Si substrate;

and,

wherein forming the diode includes forming an n+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup> and a p+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, in the first Si layer.

18. The method of claim 1 wherein forming the first wafer includes forming an n-type doped first Si layer and an n-type doped high resistance first Si substrate;

and,

wherein forming the diode includes forming an n+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup> and a p+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, in the first Si layer.

19. The method of claim 1 wherein forming the first wafer includes forming a p-type doped first Si layer and a p-type doped high resistance first Si substrate;

and,

wherein forming the diode includes forming an n+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup> and a p+ region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, in the first Si layer.

20. A method for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate, the method comprising:

forming a first wafer comprising a first Si substrate having a resistivity greater than about 100 ohm-cm, and a first Si layer with a dopant concentration in the range of about 1×

10¹⁶ to about 5×

10¹⁸ cm<sup>−

3</sup>;

forming a second wafer comprising a first silicon oxide layer and a second Si layer;

bonding the first wafer to the second wafer, forming a SOI substrate;

forming a diode with a first region, having a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, and a second region having an opposite polarity doping than the first region, with a dopant concentration in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10²⁰ cm<sup>−

3</sup>, in the first Si layer;

forming a thin-film transistor (TFT) in the second Si layer; and

,

forming interconnects between the TFT and the diode.