Integrated circuit package system with exposed interconnects

• US 20070190690A1
• Filed: 02/14/2006
• Published: 08/16/2007
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Han, Byung, Chow, Seng, Shim, Il
• Granted Patent: US 8,704,349 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.

Claims

1. An integrated circuit package system comprising:

providing a substrate having a first surface and a second surface;

mounting interconnects to the first surface;

mounting integrated circuit dies to the first surface;

embedding the interconnects and the integrated circuit dies within an encapsulant on the substrate and leaving top portions of the interconnects exposed;

attaching solder balls to the second surface; and

singulating the substrate and the encapsulant into a plurality of integrated circuit packages.

2. The system as claimed in claim 1 wherein:

embedding the interconnects and the integrated circuit dies uses a mold chase having top and bottom mold chases, the top mold chase having vacuum suction holes provided therein; and

embedding the interconnects and the integrated circuit dies includes applying a vacuum to hold a film held against the top mold chase by a vacuum.

3. The system as claimed in claim 1 wherein:

embedding the interconnects and the integrated circuit dies uses a mold chase having top and bottom mold chases, the top mold chase having a flat top inside and having vacuum suction holes provided therein; and

embedding the interconnects and the integrated circuit dies includes applying a vacuum to hold a film against the top mold chase, the film conformable to flat-topped and rounded interconnects.

4. The system as claimed in claim 1 wherein:

mounting the interconnects further comprises planarizing the interconnects to have flat-tops before or after embedding.

5. The system as claimed in claim 1 wherein:

mounting the integrated circuit dies includes mounting individual integrated circuit dies symmetrically with respect to a vertical plane; and

singulating the substrate and the encapsulant includes singulating along the vertical plane.

6. An integrated circuit package system comprising:

providing a substrate having wiring on a first surface and a second surface;

mounting interconnects to the wiring on the first surface;

mounting integrated circuit dies to the first surface;

bonding wires between the integrated circuit dies and the wiring on the first surface;

embedding the interconnects and the integrated circuit dies within an encapsulant on the substrate and leaving top portions of the interconnects exposed;

attaching solder balls to the wiring on the second surface; and

singulating the substrate and the encapsulant into a plurality of integrated circuit packages.

7. The system as claimed in claim 6 wherein:

embedding the interconnects and the integrated circuit dies uses a mold chase having top and bottom mold chases, the top mold chase having vacuum suction holes provided therein; and

embedding the interconnects and the integrated circuit dies uses a film held against the top mold chase by a vacuum to prevent encapsulant from covering the exposed top portions of the interconnects.

8. The system as claimed in claim 6 wherein:

embedding the interconnects and the integrated circuit dies uses a mold chase having top and bottom mold chases, the top mold chase having a flat top inside or a flat top with cavities inside and having vacuum suction holes provided therein; and

embedding the interconnects and the integrated circuit dies uses a film held against the top mold chase by a vacuum, the film conformable to flat-topped and rounded interconnects.

9. The system as claimed in claim 6 further comprising:

stacking the plurality of integrated circuit packages by the interconnects.

10. The system as claimed in claim 6 further comprising:

stacking one of the plurality of integrated circuit packages with other integrated circuit packages by the interconnects, wires, solder bumps, solder balls, solder joints, or studs.

11. An integrated circuit package system comprising:

a substrate having a first surface and a second surface and rounded or flat-top interconnects mounted to the first surface;

an integrated circuit die mounted to the first surface;

an encapsulant on the substrate embedding the interconnects and the integrated circuit die with top portions of the interconnects exposed; and

solder balls mounted to the second surface.

12. The system as claimed in claim 11 further comprising:

a second integrated circuit package mounted over the interconnects and having the interconnects connected to second interconnects or solder joints of the second integrated circuit package.

13. The system as claimed in claim 11 further comprising:

a second integrated circuit package having a small foot print mounted over the interconnects and having the interconnects connected to second interconnects, solder balls, or solder joints of the second integrated circuit package.

14. The system as claimed in claim 11 further comprising:

an interposer electrically connected to the interconnects; and

a second integrated circuit package mounted on and electrically connected to an interposer over the interconnects.

15. The system as claimed in claim 11 further comprising:

a heat sink shield connected to the interconnects and positioned over the integrated circuit die.

16. The system as claimed in claim 11 further comprising:

a second integrated circuit package over the interconnects; and

a heat sink shield connected to the interconnects and positioned over the integrated circuit die and the second integrated circuit package.

17. The system as claimed in claim 11 further comprising:

a die encapsulant over the integrated circuit die encapsulated by the encapsulant.

18. The system as claimed in claim 11 further comprising:

passive components positioned over and connected to the interconnects.

19. The system as claimed in claim 11 wherein:

the integrated circuit dies and the interconnects are at opposite edges of the substrate.

20. The system as claimed in claim 11 further comprising:

a second integrated circuit package over the interconnects; and

the encapsulant has a recess provided therein for electrical connections between the first and second integrated circuit packages.