Wafer level chip packaging

• US 20070190691A1
• Filed: 01/19/2007
• Published: 08/16/2007
• Est. Priority Date: 01/23/2006
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Grinman, Andrey, Rosenstein, Charles, Humpston, Giles, Ovrutsky, David, Oganesian, Vage, Hecht, Ilya, Dayan, Avi, Hazanovich, Felix, Avsian, Osher, Aksenton, Yulia, Burtzlaff, Robert, Nystrom, Michael, Reifel, Mitchell
• Granted Patent: US 7,936,062 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Claims

1. A packaged microelectronic element, comprising:

a microelectronic element having a front face and a plurality of peripheral edges bounding said front face, a device region at said front face and a contact region including a plurality of exposed contacts adjacent to at least one of said peripheral edges;

support walls overlying said front face; and

a lid mounted to said support walls above said microelectronic element, said lid having an inner surface confronting said front face, wherein at least some of said contacts are exposed beyond edges of said lid.

2. The packaged microelectronic element as claimed in claim 1, wherein said support walls are bonded by an adhesive to at least one of said front face of said microelectronic element or said inner surface of said lid.

3. The packaged microelectronic element as claimed in claim 2, wherein edges of said support walls are exposed beyond edges of said lid.

4. The packaged microelectronic element as claimed in claim 1, wherein said support walls include recesses, the recesses extending in at least a lateral direction transverse to a normal direction with respect to said front face.

5. The packaged microelectronic element as claimed in claim 1, wherein said microelectronic element includes an optoelectronic device in said device region, wherein said lid is at least partially transparent to energy at wavelengths of interest with respect to operation of said optoelectronic device.

6. The packaged microelectronic element as claimed in claim 5, wherein said lid includes a plurality of peripheral edges, said edges being oriented at an angle with respect to a normal to said front face of the microelectronic element.

7. The packaged microelectronic element as claimed in claim 1, wherein said support walls overlie a region of said microelectronic element between said device region and said contact region.

8. The packaged microelectronic element as claimed in claim 7, wherein said microelectronic element includes an optoelectronic device and at least one second device and the support walls at least partially overlie the at least one second device.

9. The packaged microelectronic element as claimed in claim 8, wherein the support walls do not overlie the optoelectronic device.

10. The packaged microelectronic element as claimed in claim 8, wherein the support walls conduct heat between the at least one second device and the lid.

11. The packaged microelectronic element as claimed in claim 8, wherein the support walls and the lid conduct heat between (i) a first one of the at least one second device at a first location of the microelectronic element and (ii) a second one of the at least one second device at a second location of the microelectronic element.

12. The packaged microelectronic element as claimed in claim 1, further comprising a material including at least one of a solid component or a liquid component disposed between said device region at said front face and an inner surface of said lid.

13. The packaged microelectronic element as claimed in claim 12, wherein the material includes a solid component and the solid component fills spaces between the device regions and the lid wafer.

14. The packaged microelectronic element as claimed in claim 12, wherein the material includes a liquid component and the liquid component fills spaces between the device regions and the lid wafer.

15. The packaged microelectronic element as claimed in claim 12, wherein the material controls a distance between a front surface of the device wafer and an inner surface of the lid wafer.

16. The packaged microelectronic element as claimed in claim 12, wherein the material applies a stress to at least one of the lid wafer or the device wafer.

17. The packaged microelectronic element as claimed in claim 12, wherein the material functions to perform at least one of heat-spreading or impeding of heat-spreading.

18. The packaged microelectronic element as claimed in claim 12, wherein the material has an optical property different from an optical property of the lid wafer.

19. The packaged microelectronic element as claimed in claim 12, wherein the material has a refractive index different from a refractive index of the lid wafer.

20. The packaged microelectronic element as claimed in claim 12, wherein the material has a mechanical motion damping property.

21. The packaged microelectronic element as claimed in claim 12, wherein the material increases dielectric strength between the lid wafer and the device wafer.

22. The packaged microelectronic element as claimed in claim 12, wherein at least a portion of the liquid component is included in liquid lenses between the device regions and the lid wafer.

23. The packaged microelectronic element as claimed in claim 12, wherein at least a portion of the liquid component is included in microdroplets contacting the device regions, and the device regions include electrowetting devices operable to electrically alter shapes of the microdroplets.

24. The packaged microelectronic element as claimed in claim 12, wherein said support walls include an adhesive, said packaged microelectronic element further comprising a dam extending from the front face of the microelectronic element between the device region and the contact region, the dam separating the adhesive from at least some of the contacts.

25. A packaged microelectronic element, comprising:

a microelectronic element including a device region and a contact region exposed at the front face, the contact region including a plurality of bond pads;

a lid joined to the microelectronic element, the lid overlying the device region;

a plurality of contacts exposed at a top surface of said packaged microelectronic element; and

a plurality of conductive traces extending upwardly from said bond pads at least partly along walls of said packaged microelectronic element to said contacts.

26. The packaged microelectronic element as claimed in claim 25, wherein said lid includes a plurality of openings exposing said bond pads, said walls include walls of said openings and said conductive traces extend in stripes along said walls of said openings.

27. The packaged microelectronic element as claimed in claim 26, wherein at least some of said openings exposes a plurality of said bond pads.

28. The packaged microelectronic element, as claimed in claim 26, wherein said microelectronic element further includes a plurality of peripheral edges bounding said front face, and at least some of said openings extend from one of said peripheral edges a horizontal dimension of said front face to an opposite one of said peripheral edges.

29. The packaged microelectronic element as claimed in claim 25, wherein said microelectronic element has a width in a widthwise horizontal dimension and a length in a lengthwise horizontal dimension, wherein said at least some openings extend said width of said microelectronic element from a first one of said peripheral edges to a second, opposite peripheral edge of said microelectronic element.

30. The packaged microelectronic element as claimed in claim 25, wherein said microelectronic element has a length in a lengthwise horizontal dimension, wherein said at least some openings extend said length of said microelectronic element from a first one of said peripheral edges to a second, opposite peripheral edge of said microelectronic element.

31. The packaged microelectronic element as claimed in claim 25, wherein said lid includes a top surface and a plurality of peripheral edges extending downwardly from said top surface of said lid, said packaged microelectronic element further comprising one or more dielectric elements overlying said contact regions and having an inner surface adjacent to one or more of said peripheral edges, said one or more dielectric elements having at least one outer surface remote from said inner surface, said at least one outer surface defining at least portions of said walls.

32. The packaged microelectronic element as claimed in claim 31, wherein said contacts are exposed at top surfaces of said dielectric elements.

33. The packaged microelectronic element as claimed in claim 25, wherein said lid includes a top surface and a plurality of peripheral edges extending away from said top surface of said lid, said contact regions of said microelectronic element being exposed beyond said peripheral edges, and said walls are defined by said edges of said lid.

34. An assembly including a packaged microelectronic element as claimed in claim 26 and a circuit panel having a plurality of terminals conductively connected through said contacts to said bond pads of the packaged microelectronic element.

35. The assembly as claimed in claim 34, wherein said terminals of said circuit panel are disposed above said packaged microelectronic element and said contacts are conductively connected to said terminals through wire bonds.

36. The assembly as claimed in claim 34, wherein said terminals of said circuit panel are disposed above said packaged microelectronic element and said contacts are conductively connected to said terminals through masses of fusible conductive material.

37. The assembly as claimed in claim 36, wherein said fusible conductive material is selected from the group consisting of solders, tin and eutectic compositions.

38. The assembly as claimed in claim 34, wherein said terminals of said circuit panel are disposed above said packaged microelectronic element and said contacts are conductively connected to said terminals through a conductive adhesive.

39. A method of making a plurality of lidded microelectronic elements, comprising:

(a) providing supporting structure overlying one of an inner surface of a lid wafer or a front face of device wafer;

(b) assembling the lid wafer with the device wafer including bonding an exposed surface of the supporting structure to the other one of the inner surface of the lid wafer or the front face of the device wafer;

(c) severing the lid wafer and the device wafer into a plurality of lidded microelectronic elements each including a lid element severed from the lid wafer and a microelectronic element severed from the device wafer.

40. The method as claimed in claim 39, wherein each microelectronic element includes a device region and the supporting structure includes a plurality of walls enclosing the device regions of the plurality of microelectronic elements.

41. The method as claimed in claim 40, wherein the contacts are disposed in contact regions adjacent to edges of the microelectronic elements.

42. The method as claimed in claim 41, wherein the device regions are disposed between the contact regions.

43. The method as claimed in claim 42, wherein the plurality of walls separate the contact regions from the device regions.

44. The method as claimed in claim 39, further comprising applying a sealant to edges of the lid elements and at least exposed surfaces of the adhesive after said step of severing.

45. The method as claimed in claim 44, further comprising mounting one of the lidded microelectronic elements to a circuit panel, wherein said sealant is applied after said step of mounting to contact conductive interconnections between the lidded microelectronic element and the circuit panel.

46. The method as claimed in claim 45, further comprising applying a sealant to overlie at least some of the contacts of the device wafer between edges of the lid elements prior to said step of severing.

47. A method of making a plurality of lidded microelectronic elements, comprising:

(a) providing a device wafer having a front surface and a plurality of contacts on the front surface;

(b) assembling an inner surface of a lid wafer to the front surface of the device wafer, the lid wafer including a first portion consisting essentially of inorganic material extending between the inner surface and an outer surface of the lid wafer and second portions including polymeric material disposed within openings in the first portion;

(c) forming apertures extending through the second portions in alignment with said contacts; and

(d) severing the assembled lid wafer and device wafer along dicing lanes into lidded microelectronic elements.

48. The method as claimed in claim 47, wherein the lid wafer is assembled with the device wafer with an adhesive between a contact region of the device wafer and the inner surface of the wafer and said method further includes removing portions of the adhesive to expose the contacts after opening the aligned areas of the second portions.

49. The method as claimed in claim 47, wherein the second portions extend partially under a lower major surface of the first portion.

50. The method as claimed in claim 49, wherein the second portions extend partially under a lower major surface of the first portion, said method further comprising providing an adhesive between the front surface of the device wafer and opposing surfaces of the second portions.

51. The method as claimed in claim 50, further comprising removing portions of the adhesive to expose the contacts after opening the aligned areas of the second portions.

52. The method as claimed in claim 51, wherein the adhesive is provided to overlie a contact region of the device wafer and said method further includes removing portions of the adhesive to expose the contacts after opening the aligned areas of the second portions.

53. The method as claimed in claim 48, wherein the adhesive has a thickness and the second portions extend a first distance in a normal direction down from a lower major surface of the first portion, the first distance being at least ten times the thickness of the adhesive.

54. The method as claimed in claim 48, further comprising roller coating exposed surfaces of the second portions with the adhesive prior to assembling the lid wafer with the device wafer.

55. The method as claimed in claim 47, wherein the inorganic material is at least substantially transparent.

56. The method as claimed in claim 54, wherein the inorganic material includes glass.

57. The method as claimed in claim 47, further comprising forming the lid wafer by steps including:

forming a plurality of blind slots in the lid wafer from a first surface selected from one of the inner surface or the outer surface;

introducing the polymeric material into the blind slots; and

reducing a thickness of the lid wafer from one of the inner and outer surfaces other than the first surface until the polymeric material becomes exposed.

58. The method as claimed in claim 47, wherein the thickness of the adhesive is less than about 5 microns.

59. The method as claimed in claim 47, wherein the apertures in the second portions are tapered such that the apertures become smaller in a direction from the outer surface towards the inner surface.

60. The method as claimed in claim 58, wherein the apertures have an oval-shaped contour in a plane defined by the outer surface of the lid wafer, each of at least some of the apertures being aligned with a plurality of the contacts.

61. The method as claimed in claim 58, wherein adjacent ones of the apertures have a first pitch smaller than a second pitch which would be realizable in adjacent ones of second apertures, were the second apertures to be formed in the first portion, given the thickness and the material of the first portion.

62. The method as claimed in claim 47, wherein the first portion includes a plurality of island portions, each island portion spaced from each one of the island portions adjacent thereto by one of the second portions.

63. A method of assembling a semiconductor element including an optoelectronic device with a circuit panel, comprising:

a) optically aligning a vacuum head with an optoelectronic device on a front face of semiconductor element using light returning from a front face of the semiconductor element through an at least partially transparent lid element overlying the semiconductor element; and

b) transporting the lidded semiconductor element with the vacuum head to a mounting location on the circuit panel.

64. The method as claimed in claim 63, wherein the lid element includes an exposed outer surface aligned with the optoelectronic device and the vacuum head engages the exposed outer surface.