ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS
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Abstract
Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
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Citations
32 Claims
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1-21. -21. (canceled)
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22. An enhanced silicon-on-insulator (SOI) transistor comprising:
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a thin buried oxide (BOX) layer;
an active channel region over said thin buried oxide (BOX) layer;
a gate dielectric and a gate electrode over said active channel region;
source/drain regions adjacent said active channel region;
said source/drain regions having selective strain for enhanced carrier mobility for both P-channel and N-channel devices; and
a thick self-aligned buried oxide (BOX) region under said source/drain regions. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification