Implantable biomedical chip with modulator for a wireless neural stimulation system

• US 20070191888A1
• Filed: 02/13/2006
• Published: 08/16/2007
• Est. Priority Date: 02/13/2006
• Status: Active Grant

• Current Assignee: National Sun Yat-sen University
• Original Assignee: National Sun Yat-sen University
• Inventors: Wang, Chua-Chin, Lee, Tzung-Je
• Granted Patent: US 7,627,371 B2
• Time in Patent Office: Days
• US Class Current: 607/2
• CPC Class Codes: A61N 1/32 alternating or intermittent currents applying electric fields by inductive or capacitive coupling A61N1/40; microwave apparatus A61N5/02
• CPC Class Codes: A61N 1/36071 Pain
• CPC Class Codes: A61N 1/3787 from an external energy source

Abstract

The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.

Claims

1. An implantable biomedical chip with modulator for a wireless neural stimulating system, comprising:

a power regulator, for receiving power from a receiver coil and providing power;

a demodulator, for demodulating an input signal from the receiver coil to a demodulated signal;

a baseband circuit, for decoding the demodulated signal to at least one control signal;

a D/A converter, for converting the control signal to a stimulating current;

an instrumentation amplifier, for amplifying and filtering a neural signal;

an A/D converter, for converting the neural signal from the instrumentation amplifier to a digital neural signal; and

a modulator, the for modulating the digital neural signal to an output signal.

2. The implantable biomedical chip according to claim 1, further comprising a clock generator and power-on reset circuit, the clock generator used for generating a clock signal to the baseband circuit, the power-on reset circuit used for generating a power-on reset signal to the baseband circuit.

3. The implantable biomedical chip according to claim 1, wherein the baseband circuit comprises:

a mixed-signal module, for generating a built-in clock signal and a built-in reset signal;

a data and clock recovery circuit, for generating a recovered clock signal and recovering the demodulated signal to a recovered packet according to the built-in clock signal and the built-in reset signal;

a serial to parallel converter, for converting the recovered packet into a parallel recovered packet;

a decoder, for decoding the recovered clock and the parallel recovered packet and generating an address control signal, a magnitude control signal and a polarity control signal.

4. The implantable biomedical chip according to claim 3, wherein the mixed-signal module comprises:

an oscillator and a built-in reset circuit, the oscillator is used for generating the built-in clock signal, the built-in reset circuit is used for generating the built-in reset signal.

5. The implantable biomedical chip according to claim 1, wherein the modulator is a load-shift keying modulator.

6. The implantable biomedical chip according to claim 5, wherein the modulator comprises:

a transistor and a capacitance.

7. A state transition method for an implantable biomedical chip, comprising the steps of:

(a) transiting a zero state to a first state according to a built-in reset signal;

(b) transiting the first state to a second state according to a synchronization packet;

(c) transiting the second state to a third state according to a start packet; and

(d) transiting the third state to the first state according to an end packet.

8. The state transition method according to claim 7, wherein when the built-in reset signal is at high level, the zero state is transited to the first state.

9. The state transition method according to claim 7, further comprising a step of:

transiting the first state to the zero state when the built-in reset signal is at low level.

10. The state transition method according to claim 7, further comprising a step of:

transiting the second state to the zero state when the built-in reset signal is at low level.

11. The state transition method according to claim 7, further comprising a step of:

transiting the third state to the zero state when the built-in reset signal is at low level.