SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS

• US 20070192563A1
• Filed: 02/08/2007
• Published: 08/16/2007
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Wang, David, Smith, Michael, Schakel, Keith, Rajan, Suresh, Weber, Frederick
• Granted Patent: US 9,632,929 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit capable of communication with a plurality of memory circuits and a system, the interface circuit operable to translate an address associated with a command communicated between the system and the memory circuits.

2. The sub-system as set forth in claim 1, wherein the translation includes shifting the address.

3. The sub-system as set forth in claim 1, wherein the memory circuits include physical memory circuits, and the interface circuit is operable to simulate at least one virtual memory circuit.

4. The sub-system as set forth in claim 3, wherein the at least one virtual memory circuit has a different number of row addresses than the physical memory circuits.

5. The sub-system as set forth in claim 3, wherein the at least one virtual memory circuit has a greater number of row addresses than the physical memory circuits.

6. The sub-system as set forth in claim 4, wherein the translation is performed as a function of the difference in the number of row addresses.

7. The sub-system as set forth in claim 4, wherein the translation translates the address to reflect the number of row addresses of the at least one virtual memory circuit.

8. The sub-system as set forth in claim 1, wherein the translation results in sub-row activation.

9. The sub-system as set forth in claim 1, wherein the translation translates the address as a function of a column address and a row address.

10. The sub-system as set forth in claim 1, wherein the command includes a row-access command, and the translation ensures that a column-access command addresses an open bank.

11. The sub-system as set forth in claim 1, wherein the command includes a row-access command, and the translation is performed as a function of an expected arrival time of a column-access command.

12. The sub-system as set forth in claim 1, wherein the interface circuit is further operable to delay the command communicated between the system and the memory circuits.

13. The sub-system as set forth in claim 1, wherein the command includes at least one of a row-access command and a column-access command.

14. The sub-system as set forth in claim 1, wherein the translation is transparent to the system.

15. The sub-system as set forth in claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

16. The sub-system as set forth in claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

17. A method comprising:

interfacing a plurality of memory circuits and a system; and

translating an address associated with a command communicated between the system and the memory circuits.

18. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the memory circuits, the interface circuit operable to translate an address associated with a command communicated between the system and the memory circuits.

19. The system as set forth in claim 18, wherein the memory circuits and the interface circuit are positioned on a dual in-line memory module (DIMM).

20. The system as set forth in claim 18, wherein the memory circuits and the interface circuit are positioned on a memory module that remains in communication with a processor via a bus.