Asynchronous power saving computer

• US 20070192646A1
• Filed: 02/16/2006
• Published: 08/16/2007
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Moore, Charles
• Granted Patent: US 7,904,695 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).

Claims

1. A computer, comprising:

a processor for executing instructions from an instruction area; and

a sequencer for providing a pulse to advance from a presently executed instruction to a next instruction;

wherein

said instruction includes a bit for providing an input to the sequencer such that the sequencer is triggered into action when the bit is set.

2. The computer of claim 1, wherein:

the bit is set when it is a ‘

1’

.

3. The computer of claim 1, wherein:

the instructions are part of a larger instruction word.

4. The computer of claim 1, wherein:

when said bit for providing an input to the sequencer is not set then the sequencer is not triggered into action.

5. The computer of claim 4, wherein:

when said bit for providing an input to the sequencer is not set then a first communications status line is set between the computer and a second computer.

6. The computer of claim 5, wherein:

said first communications status line is a write line.

7. The computer of claim 5, wherein:

said first communications status line is a read line.

8. The computer of claim 5, wherein:

when a second communications status line is set then data is transferred between the computer and the second computer.

9. The computer of claim 8, wherein:

data is transferred from the computer to the second computer.

10. The computer of claim 8, wherein:

the data includes an instruction.

11. The computer of claim 8, wherein:

when the second communications status line is set then an input is provided to the sequencer such that the sequencer is triggered into action.

12. A method for causing a computer to temporarily reduce its power consumption, comprising:

(a) causing the computer to stop operation when a communication is attempted with an outside entity; and

(b) causing the computer to resume operation when completion of the communication with the outside entity is acknowledged.

13. The method of claim 12, wherein:

the outside entity is another computer.

14. The method of claim 12, wherein:

both the computer and the outside entity are on a single chip.

15. The method of claim 12, wherein:

when the computer stops operation it also alters the status of a first status line between the computer and the outside entity.

16. The method of claim 12, wherein:

communication with the outside entity is acknowledged when both of two communications status lines are set to a same status.

17. The method of claim 12, wherein:

when the computer operation is stopped then a first one of two status lines between the computer and the outside entity is set; and

when the second one of the two status lines is set then data is communicated and then operation of the computer is resumed.

18. The method of claim 12, wherein:

a sequencer produces a pulse to cause execution of each of a plurality of instructions; and

no such pulse is immediately produced when the communication is attempted with the outside entity.

19. The method of claim 18, wherein:

when completion of the communication with the outside entity is acknowledged then a pulse is produced to cause execution of a next instruction.

20. In a computer for executing instructions wherein at least some of the instructions are instructions to communicate with an outside entity, an improvement comprising:

means for causing the computer to stop when an instruction to communicate with the outside entity is attempted; and

means for causing the computer to restart when the instruction to communicate with the outside entity is completed.

21. The improvement of claim 20, wherein:

the means for causing the computer to stop when an instruction to communicate with the outside entity is attempted includes a pulse generating apparatus for generating a pulse when each instruction is executed, except that when the instruction is an instruction to communicate with the outside entity then no such pulse is generated.

22. The improvement of claim 21, wherein:

the means for causing the computer to restart when the instruction to communicate with the outside entity is completed includes a means for causing the pulse generating apparatus to generate a pulse.

23. The improvement of claim 21, wherein:

the pulse generating apparatus is caused to generate a pulse when the outside entity acknowledges completion of the communication.