GATE STACKS

• US 20070194385A1
• Filed: 08/08/2006
• Published: 08/23/2007
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Dale W. Martin, Deborah A. Tucker, Michael C. Triplett, Steven M. Shank
• Inventors: Shank, Steven M., Tucker, Deborah A., Martin, Dale W., Triplett, Michael C.
• Granted Patent: US 7,378,712 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

Claims

1. A semiconductor structure, comprising:

(a) a semiconductor region;

(b) a gate stack on top of the semiconductor region, the gate stack including

(i) a gate dielectric region on top of the semiconductor region,

(ii) a first gate polysilicon region on top of the gate dielectric region, and

(iii) a second gate polysilicon region on top of the first gate polysilicon region, the second gate polysilicon region being doped with a type of dopants; and

(c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack,

wherein the diffusion barrier region is sandwiched between the gate stack and the spacer oxide region,

wherein the diffusion barrier region is in direct physical contact with both the first and second gate polysilicon regions, and

wherein the diffusion barrier region comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

2. The semiconductor structure of claim 1, wherein the second gate polysilicon region is doped with n-type dopants.

3. The semiconductor structure of claim 1, wherein the diffusion barrier region comprises oxynitride silicon.

4. The semiconductor structure of claim 1, wherein a first thickness of a first region of the spacer oxide region corresponding to the first gate polysilicon region and a second thickness of a second region of the spacer oxide region corresponding to the second gate polysilicon region are substantially identical.

5. A semiconductor structure, comprising:

(a) a semiconductor substrate;

(b) a gate stack on top of the semiconductor substrate, the gate stack including

(i) a gate dielectric region on top of the semiconductor substrate,

(ii) a first gate polysilicon region on top of the gate dielectric region, and

(iii) a second gate polysilicon region on top of the first gate polysilicon region, the second gate polysilicon region being heavily doped with a type of dopants; and

(c) a first diffusion barrier region and a first spacer oxide region on a first side wall of the gate stack,

wherein the first diffusion barrier region is sandwiched between the gate stack and the first spacer oxide region, and

wherein the first diffusion barrier region is in direct physical contact with both the first and second gate polysilicon regions; and

(d) a second diffusion barrier region and a second spacer oxide region on a second side wall of the gate stack,

wherein the second diffusion barrier region is sandwiched between the gate stack and the second spacer oxide region,

wherein the second diffusion barrier region is in direct physical contact with both the first and second gate polysilicon regions, and

wherein the first and second diffusion barrier regions comprise a material having a property of preventing a diffusion of oxygen-containing materials through the first and second diffusion barrier regions.

6. The structure of claim 5, wherein the second gate polysilicon region is doped with n-type dopants.

7. The structure of claim 5, wherein the first and second diffusion barrier regions comprise oxynitride silicon.