Integrated circuit architecture for reducing interconnect parasitics

• US 20070194453A1
• Filed: 01/27/2006
• Published: 08/23/2007
• Est. Priority Date: 01/27/2006
• Status: Abandoned Application

• Current Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Chakraborty, Kanad, Xu, Bingxiong, Zhou, Xingling
• Application Number:
  US11/341,747
• Publication Number:
  US 20070194453A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]

Abstract

An integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the first semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip. The first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and vice versa. The first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.

Claims

1. An integrated circuit, comprising:

a first semiconductor chip including one or more circuits thereon for performing substantially core logic functions, the first semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits; and

at least a second semiconductor chip including one or more circuits thereon for performing substantially input/output interface functions, the second semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip, the signal pads on the second semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip to thereby reduce interconnect parasitics in the integrated circuit;

wherein the first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and at least a portion of at least one of the one or more circuits on the second semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the first semiconductor chip, and wherein the first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.

2. The integrated circuit of claim 1, wherein the first semiconductor chip does not include circuitry for performing input/output interface functions.

3. The integrated circuit of claim 1, wherein the signal pads on first semiconductor chip are electrically connected to respective signal pads on the second semiconductor chip using a plurality of corresponding conductive structures.

4. The integrated circuit of claim 1, wherein the signal pads on first semiconductor chip are electrically connected to respective signal pads on the second semiconductor chip using a plurality of corresponding solder bumps.

5. The integrated circuit of claim 1, wherein the first semiconductor chip comprises core logic functional circuitry.

6. The integrated circuit of claim 1, wherein the second semiconductor chip comprises input/output functional circuitry.

7. The integrated circuit of claim 1, wherein the first semiconductor chip comprises substantially digital circuitry and the second semiconductor chip comprises substantially analog circuitry.

8. The integrated circuit of claim 1, wherein at least one of voltage supply and ground connections to the first semiconductor chip are separate from at least one of voltage supply and ground connections, respectively, to the second semiconductor chip.

9. The integrated circuit of claim 1, wherein the first and second semiconductor chips are arranged relative to each other such that an upper surface of the first semiconductor chip faces an upper surface of the second semiconductor chip.

10. The integrated circuit of claim 1, wherein at least one of:

(i) one or more parameters of the first semiconductor fabrication process are selectively adjusted to independently optimize a functional performance of the first semiconductor chip; and

(ii) one or more parameters of the second semiconductor fabrication process are selectively adjusted to independently optimize a functional performance of the second semiconductor chip.

11. The integrated circuit of claim 1, wherein the one or more circuits on the second semiconductor chip comprises at least one of a serializer/deserializer, a phase-locked loop, an analog-to-digital converter, a digital-to-analog converter, and memory.

12. The integrated circuit of claim 1, wherein the integrated circuit is configured such that a functionality thereof is selectively changed by substituting the first semiconductor chip with another semiconductor chip having a functionality different than that of the first semiconductor chip, the other semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits, the signal pads on the other semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the second semiconductor chip, the other semiconductor chip and the second semiconductor chip being mutually functionally dependent on one another.

13. A packaged multiple-die integrated circuit device, comprising:

a die-attachment substrate including a plurality of electrical contacts providing external electrical connection to the package;

a first semiconductor chip including one or more circuits thereon for performing substantially core logic functions, the first semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits;

at least a second semiconductor chip including one or more circuits thereon for performing substantially input/output interface functions, the second semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip, the signal pads on the second semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip to thereby reduce interconnect parasitics in the integrated circuit; and

an encapsulant material enclosing the first and second semiconductor chips and covering at least a portion of the die-attachment substrate such that the plurality of electrical contacts remains at least partially uncovered;

wherein the first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and at least a portion of at least one of the one or more circuits on the second semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the first semiconductor chip, and wherein the first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.