Integrated circuit architecture for reducing interconnect parasitics
First Claim
1. An integrated circuit, comprising:
- a first semiconductor chip including one or more circuits thereon for performing substantially core logic functions, the first semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits; and
at least a second semiconductor chip including one or more circuits thereon for performing substantially input/output interface functions, the second semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip, the signal pads on the second semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip to thereby reduce interconnect parasitics in the integrated circuit;
wherein the first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and at least a portion of at least one of the one or more circuits on the second semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the first semiconductor chip, and wherein the first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
1 Assignment
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Accused Products
Abstract
An integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the first semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip. The first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and vice versa. The first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
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Citations
13 Claims
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1. An integrated circuit, comprising:
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a first semiconductor chip including one or more circuits thereon for performing substantially core logic functions, the first semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits; and
at least a second semiconductor chip including one or more circuits thereon for performing substantially input/output interface functions, the second semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip, the signal pads on the second semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip to thereby reduce interconnect parasitics in the integrated circuit;
wherein the first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and at least a portion of at least one of the one or more circuits on the second semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the first semiconductor chip, and wherein the first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A packaged multiple-die integrated circuit device, comprising:
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a die-attachment substrate including a plurality of electrical contacts providing external electrical connection to the package;
a first semiconductor chip including one or more circuits thereon for performing substantially core logic functions, the first semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits;
at least a second semiconductor chip including one or more circuits thereon for performing substantially input/output interface functions, the second semiconductor chip including a plurality of signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip, the signal pads on the second semiconductor chip being substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip to thereby reduce interconnect parasitics in the integrated circuit; and
an encapsulant material enclosing the first and second semiconductor chips and covering at least a portion of the die-attachment substrate such that the plurality of electrical contacts remains at least partially uncovered;
wherein the first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and at least a portion of at least one of the one or more circuits on the second semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the first semiconductor chip, and wherein the first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
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Specification