Electronic device and method

• US 20070194804A1
• Filed: 02/23/2006
• Published: 08/23/2007
• Est. Priority Date: 02/23/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kase, Kiyoshi, Tran, Dzung
• Granted Patent: US 7,768,296 B2
• Time in Patent Office: Days
• US Class Current: 326/27
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

Claims

1. An electronic device comprising:

a buffer comprising an input and an output;

an interconnect coupled to the output of the buffer; and

a current boost module comprising a first input coupled to the buffer input, a second input coupled to the interconnect, and an output coupled to the interconnect the current boost module to detect when the buffer is transitioning between logic states and to provide a boost current to facilitate a signal transition at the interconnect in response to detecting the transition.

2. The device as in claim 1, further comprising a receive/drive device comprising an input coupled to the interconnect, and an output, the receive/drive device configured to produce an output signal at its output responsive to a signal at its input.

3. The device as in claim 2, wherein the input of the receive/drive device is responsive to a voltage that varies between 0 volts and 1.3 volts.

4. The device as in claim 3, wherein the receive/drive device is a data bus driver.

5. The device as in claim 3, further comprising one of a video or audio module coupled to the output of the receive/drive device.

6. The device as in claim 3, wherein a threshold voltage of the receive/drive device is between approximately 0.5 volts and 0.7 volts.

7. The device as in claim 1, further comprising:

wherein the current boost module further provides the boost current in response to detecting the transition between logic states has not completed.

8. A method for reducing switching delay of an electronic device comprising:

detecting a first signal at an input of a buffer;

detecting a second signal at an output of the buffer;

providing a boost current to an interconnect coupled to the output of the buffer when it is determined in response to detecting the first and second signal that the buffer is in transition between logic states.

9. The method of claim 8, wherein providing the boost current occurs only during a portion of the buffer'"'"'s transition between logic states.

10. The method of claim 8, wherein the input signal has a voltage range from between 0 volts and 1.3 volts.

11. The method of claim 8, wherein providing the boost current occurs between when an input signal on the input of the buffer is received and when an output of the buffer transitions to a different state.

12. The method of claim 11, wherein providing the current boost increases a slew rate at the interconnect to reduce a signal transition delay between the input of the buffer and a corresponding signal transition at the output of a device having an input coupled to the interconnect.

13. The method of claim 8, wherein providing the boost current increases a slew rate at the interconnect by more than approximately 0.5V/ns.

14. The method of claim 8, further comprising transmitting data over a multi-destination data bus via a receive/drive device that is responsive to a signal at the interconnect.

15. The method of claim 8, wherein boosting the current only occurs during a portion of the second signal'"'"'s transition.

16. The method of claim 15, wherein the portion of the second signal'"'"'s transition during which boosting the current occurs is based upon a voltage threshold of a transistor.

17. A method for reducing switching delay of an electronic device comprising:

providing an input signal to a first buffer and a boost module;

providing an output signal from the first buffer to provide a first current to an interconnect coupled to an input of a second buffer; and

providing a second current from the boost module to the interconnect to facilitate transition of the second buffer to a different logic state.

18. The method of claim 17, wherein the input signal has a voltage range from between 0 volts and 1.3 volts.

19. The method of claim 17, wherein providing the second current increases a slew rate of a signal at the interconnect.

20. The method of claim 17, wherein providing the second current reduces a signal transition delay from an input of the first buffer to the output of the second buffer by more than ten percent.