Over voltage clamp

• US 20070195566A1
• Filed: 02/23/2006
• Published: 08/23/2007
• Est. Priority Date: 02/23/2006
• Status: Active Grant

• Current Assignee: American Power Conversion Corporation (Schneider Electric SE)
• Original Assignee: American Power Conversion Corporation (Schneider Electric SE)
• Inventors: Nielsen, Henning, Petersen, Jesper
• Granted Patent: US 7,583,521 B2
• Time in Patent Office: Days
• US Class Current: 363/53
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/28 using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
• CPC Class Codes: H02M 7/10 arranged for operation in series, e.g. for multiplication of voltage

Abstract

A clamp circuit for use in a DC/DC voltage converter having a first converter output including a first node and a second node, and a second converter output including a third node a fourth node. The clamp circuit includes a positive voltage output node coupled to the first node, a negative voltage output node coupled to the fourth node, a neutral voltage output node, a first diode coupled between the positive voltage output node and the third node, a second diode coupled between the negative voltage output node and the second node, a first inductor coupled between the second diode and the neutral voltage output node, and a second inductor coupled between the first diode and the neutral voltage output node.

Claims

1. A clamp circuit for use in a DC/DC voltage converter having a first converter output including a first node and a second node, and a second converter output including a third node a fourth node, the clamp circuit comprising:

a positive voltage output node coupled to the first node;

a negative voltage output node coupled to the fourth node;

a neutral voltage output node;

a first diode coupled between the positive voltage output node and the third node;

a second diode coupled between the negative voltage output node and the second node;

a first inductor coupled between the second diode and the neutral voltage output node; and

a second inductor coupled between the first diode and the neutral voltage output node.

2. The clamp circuit of claim 1 wherein an anode of the first diode is coupled to the second inductor, a cathode of the first diode is coupled to the positive voltage output node, an anode of the second diode is coupled to the negative output voltage node, and a cathode of the second diode is coupled to the first inductor.

3. The clamp circuit of claim 2 further comprising a first capacitor and a second capacitor, the first capacitor being coupled between the positive voltage output node and the neutral voltage output node, the second capacitor being coupled between the neutral voltage output node and the negative voltage output node.

4. The clamp circuit of claim 2 further comprising:

a third diode coupled between the first and second nodes; and

a fourth diode coupled between the third and fourth nodes.

5. The clamp circuit of claim 4 wherein the second diode is configured to conduct a current when a voltage across the third diode exceeds a predetermined threshold.

6. The clamp circuit of claim 4 wherein the first diode is configured to conduct a current when a voltage across the fourth diode exceeds a predetermined threshold.

7. The clamp circuit of claim 6 wherein the second diode is configured to conduct a current when a voltage across the fourth diode exceeds the predetermined threshold.

8. A system for receiving DC power of a first level and providing DC power of a second level, the system including first, second, and third outputs, the system comprising:

a transformer;

a primary module configured to receive DC power of a first level and to provide a quasi-square wave to the transformer;

a first rectifier bridge coupled to the transformer, and including first and second nodes, the first node being coupled to the first output;

a second rectifier bridge coupled to the transformer, and including third and fourth nodes, the fourth node being coupled to the third output; and

a voltage clamp arrangement coupled to the first and second rectifier bridges, the clamp arrangement comprising;

a first diode coupled between the first node and the third node; and

a second diode coupled between the second node and the fourth node;

wherein the first diode is configured to direct energy from the first rectifier bridge to the third output if the voltage across the first rectifier bridge exceeds a first threshold;

wherein the second diode is configured to direct energy from the second rectifier bridge to the first output if the voltage across the second rectifier bridge exceeds a second threshold.

9. The system of claim 8 further comprising:

a first inductor coupled between the second node and the second output; and

a second inductor coupled between the third node and the second output.

10. The system of claim 8 further comprising:

a first capacitor coupled between the first output and the second output; and

a second capacitor coupled between the second output and the third output.

11. The system of claim 8 wherein the first diode includes an anode and a cathode, and the second diode includes an anode and a cathode, wherein the anode of the first diode is coupled to the third node, the cathode of the first diode is coupled to the first output, the anode of the second diode is coupled to the fourth node, and the cathode of the second diode is coupled to the second node.

12. The system of claim 8 further comprising:

a third diode coupled between the first and second nodes; and

a fourth diode coupled between the third and fourth nodes.

13. A controller portion for use with a DC/DC voltage converter having first and second transformers, first and second switch transistor bridges being configured to provide quasi-square waves to the first and second transformer portions, a positive voltage output node, and a negative voltage output node, the controller comprising:

a first input node configured to be coupled to the positive voltage output node;

a second input node configured to be coupled to the negative voltage output node; and

a control circuit coupled to the first and second input nodes, configured to be coupled to the transistor bridges, and configured to provide output signals, in response to voltages applied to the first and second input nodes, for use by the transistor bridges, to produce quasi-square waves of desired duty cycles.

14. The controller of claim 13 wherein the control circuit is configured to control the duty cycles of the quasi-square waves provided to the transformer portions in response to a voltage difference between the first and second input nodes.

15. The controller of claim 13 wherein the control circuit is configured to decrease the duty cycle of the quasi-square wave provided to the first transformer portion in response to the voltage applied to the first input node increasing relative to the voltage applied to the second input node.

16. The controller of claim 13 wherein the control circuit is configured to increase the duty cycle of the quasi-square wave provided to the second transformer portion in response to the voltage applied to the second input node increasing relative to the voltage applied to the first input node.

17. The controller circuit of claim 13 wherein the control circuit comprises:

first and second integrator circuits;

first and second amplifiers, the first inverting amplifier being coupled to the first integrator circuit, the second inverting amplifier being coupled to the second integrator circuit, the second amplifier being an inverting amplifier;

a first diode coupled between an output of the first inverting amplifier and a negative input of the second integrator circuit; and

a second diode coupled between an output of the second inverting amplifier and a negative input of the first integrator circuit.

18. The controller circuit of claim 17 wherein the output of the first amplifier is coupled to the negative input node of the first integrator circuit, and the output of the second amplifier is coupled to the negative input node of the second integrator circuit.

19. The controller circuit of claim 18 wherein the first diode is coupled between the output of the first amplifier and the output of the second amplifier.