Memory module with memory stack and interface with enhanced capabilities

• US 20070195613A1
• Filed: 02/05/2007
• Published: 08/23/2007
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh N., Smith, Michael J.S.
• Granted Patent: US 8,089,795 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

Claims

1. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer circuit, coupled to a host system, for interfacing said memory stack to said host system for transforming one or more physical parameters between said DRAM integrated circuits and said host system.

2. The memory module as set forth in claim 1, wherein:

said memory module further comprises a dual rank DIMM for mounting said DRAM integrated circuits; and

said buffer circuit further comprises a circuit to transform the electrical loading of said dual rank DIMM into a single rank DIMM.

3. The memory module as set forth in claim 1, wherein said buffer comprises a module to monitor the power supply rails, such as voltage rails or voltage planes, and detect a catastrophic event, such as a power supply failure.

4. The memory module as set forth in claim 1, wherein said buffer circuit comprises a module to monitor the state of the signals from a memory controller of said host system to detect a system crash.

5. The memory module as set forth in claim 1, wherein said buffer circuit further comprises a module to ignore signals from a memory controller of said host system, to generate legal combinations of signals to maintain data, stored in said DRAM integrated circuits, and to generate periodic refresh signals for said DRAM integrated circuits upon detection of a system crash.

6. The memory module as set forth in claim 1, wherein said buffer circuit further comprises a module to compensate for any skews or timing variations in signals transferred between said host system and said DRAM memory integrated circuits.

7. The memory module as set forth in claim 1, wherein said buffer circuit comprises:

a plurality of I/O pins; and

a circuit to control a slew rate, pull-up capability or strength, and pull-down capability or strength to at least one of said I/O pins.

8. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer circuit, coupled to a host system, for interfacing said memory stack to said host system for configuring one or more of said DRAM integrated circuits in said memory stack.

9. The memory module as set forth in claim 8, wherein:

said DRAM memory integrated circuits comprise slow DRAM memory integrated circuits; and

said buffer circuit for emulating high-speed DRAM operation to said host system.

10. The memory module as set forth in claim 8, wherein said buffer circuit comprises:

a plurality of integrated circuit select inputs; and

circuit for configuring a plurality of DRAM integrated circuits in said memory stack to match a number of valid integrated circuit select inputs received by said buffer circuit from said host system.

11. The memory module as set forth in claim 8, wherein:

said memory stack comprises at least one non-volatile memory device; and

said buffer circuit further for copying data from at least one of said DRAM memory integrated circuits to said non-volatile memory upon detection of a catastrophic event.

12. The memory module as set forth in claim 8, wherein:

said buffer circuit further for exposing a greater number of banks than a number of banks in said memory stack.

13. The memory module as set forth in claim 8, wherein:

said buffer circuit further for exposing a lesser number of banks than a number of banks in said memory stack.

14. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer circuit, coupled to a host system, for interfacing said memory stack to said host system for providing at least one function to said host system.

15. The memory module as set forth in claim 14, wherein:

said memory module further comprises a DIMM, including a plurality of slots, for mounting said DRAM integrated circuits; and

said buffer circuit comprises a circuit to permit said host system to maintain open a maximum number of memory pages even though a number of DIMM slots are fewer than a maximum number of DIMM slots said host system is capable of supporting.

16. The memory module as set forth in claim 14, wherein said buffer circuit comprises a circuit for allocating at least one of said DRAM integrated circuits to a first operating system or thread in an active state and allocating at least one other of said DRAM integrated circuits to a second operating system or threads, which is not currently being executed, in a low power or power down mode.

17. The memory module as set forth in claim 14, wherein said buffer circuit for mapping addresses for said host system to access data in said DRAM integrated circuits.

18. The memory module as set forth in claim 17, wherein said addresses comprise linear addresses.

19. The memory module as set forth in claim 17, wherein said addresses comprise bank-slice addresses.

20. The memory module as set forth in claim 14, wherein the buffer integrated circuit, includes integrated circuits to enable the buffer integrated circuit to gang a plurality of DRAM devices operating at a first clock speed to emulate to the host system one or more DRAM integrated circuits operating at a second clock speed, the first clock speed slower than the second clock speed.

21. A computer system comprising:

host system;

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer circuit, coupled to said host system, for interfacing said memory stack to said host system for transforming one or more physical parameters between said DRAM integrated circuits and said host system.

22. The computer system as set forth in claim 21, wherein:

said memory module further comprises a dual rank DIMM for mounting said DRAM integrated circuits; and

said buffer circuit further comprises a circuit to transform the electrical loading of said dual rank DIMM into a single rank DIMM.

23. A printed circuit motherboard comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer circuit, coupled to a host system, for interfacing said memory stack to said host system for transforming one or more physical parameters between said DRAM integrated circuits and said host system.

24. The printed circuit motherboard as set forth in claim 23, wherein:

said printed circuit motherboard further comprises a dual rank DIMM for mounting said DRAM integrated circuits; and

said buffer circuit further comprises a circuit to transform the electrical loading of said dual rank DIMM into a single rank DIMM.

25. The printed circuit motherboard as set forth in claim 23, wherein said buffer comprises a module to monitor the power supply rails, such as voltage rails or voltage planes, and detect a catastrophic event, such as a power supply failure.

26. The printed circuit motherboard as set forth in claim 23, wherein said buffer circuit comprises a module to monitor the state of the signals from a memory controller of said host system to detect a system crash.

27. The printed circuit motherboard as set forth in claim 23, wherein said buffer circuit further comprises a module to ignore signals from a memory controller of said host system, to generate legal combinations of signals to maintain data, stored in said DRAM integrated circuits, and to generate periodic refresh signals for said DRAM integrated circuits upon detection of a system crash.

28. The printed circuit motherboard as set forth in claim 23, wherein said buffer circuit further comprises a module to compensate for any skews or timing variations in signals transferred between said host system and said DRAM memory integrated circuits.

29. The printed circuit motherboard as set forth in claim 23, wherein said buffer circuit comprises:

a plurality of I/O pins; and

a circuit to control a slew rate, pull-up capability or strength, and pull-down capability or strength to at least one of said I/O pins.