METHOD AND APPARATUS FOR INCREASING YIELD IN A MEMORY CIRCUIT

• US 20070195621A1
• Filed: 04/27/2007
• Published: 08/23/2007
• Est. Priority Date: 01/12/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lu, Yu, Lamorey, Mark, Nowak, Janusz
• Granted Patent: US 7,352,639 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the first mode, the control circuitry is operative to apply a first signal to a selected memory cell in the memory circuit for reading a logic state of the selected memory cell and to determine whether or not the selected memory cell is shorted. In the second mode, the control circuitry is operative to apply a second signal to a selected memory cell which has been determined to be shorted for initiating a repair of the selected memory cell, the second signal being greater in magnitude than the first signal.

Claims

1. A method for repairing one or more shorted memory cells in a memory circuit, the method comprising the steps of:

setting a signal to be applied to a selected memory cell in the memory circuit to a first value;

setting a current address to a value corresponding to a current selected memory cell in the memory circuit;

reading a logic state of the current selected memory cell with the signal at the first value and determining whether or not the current selected memory cell is shorted;

when the current selected memory cell is determined to be shorted, initiating a repair of the shorted memory cell, and repeating the steps of reading the logic state of the current selected memory cell and determining whether or not the selected memory cell is shorted; and

when the current selected memory cell is determined to be not shorted, setting the current address to a value corresponding to a new current selected memory cell which has not been previously read, and repeating the steps of reading the logic state of the current selected memory cell and determining whether or not the selected memory cell is shorted.

2. The method of claim 1, wherein the step of initiating a repair of the shorted memory cell comprises the steps of:

setting the signal to be applied to a selected memory cell to a second value, the second value being greater in magnitude than the first value;

applying the signal at the second value to the current selected memory cell which has been determined to be shorted; and

setting the signal to be applied to a selected memory cell to the first value.

3. The method of claim 2, wherein the step of applying the signal comprises reading a logic state of the current selected memory cell with the signal at the second value.

4. The method of claim 1, wherein the step of determining whether or not the current selected memory cell is shorted comprises determining whether the current selected memory cell is functioning within a prescribed range of operation.

5. The method of claim 1, wherein the step of determining whether or not the current selected memory cell is shorted comprises the steps of:

applying a voltage of a known magnitude across the current selected memory cell and measuring a resulting current flowing through the selected memory cell; and

comparing the resulting current flowing through the selected memory cell with a known reference current.

6. The method of claim 5, wherein the known reference current is set to a midrange distribution between a low logic state and a high logic state.

7. The method of claim 5, wherein the known reference current is set above a current value corresponding to a lowest expected resistance of an acceptable memory cell.

8. The method of claim 1, further comprising the step of storing the current address of the current selected memory cell when it is determined that the current selected memory cell is shorted.

9. The method of claim 1, wherein the step of initiating a repair of the shorted memory cell comprises the steps of:

tracking a number of times a repair has been initiated on the shorted memory cell; and

when the number of times a repair has been initiated on the shorted memory cell exceeds a prescribed value, setting the current address to a value corresponding to a new current selected memory cell which has not been previously read, and repeating the steps of reading the logic state of the current selected memory cell and determining whether or not the selected memory cell is shorted.

10. The method of claim 1, further comprising the steps of:

after the step of initiating a repair of the shorted memory cell, determining whether or not the current selected memory cell has been repaired; and

when it is determined that the current selected memory cell has not been repaired, repeating the step of initiating a repair of the shorted memory cell.

11. The method of claim 1, wherein the step of initiating a repair of the shorted memory cell comprises the step of performing a plurality of successive repair cycles on the selected memory cell.

12. The method of claim 1, wherein the step of initiating a repair of the shorted memory cell comprises the steps of:

setting the signal to be applied to a selected memory cell to a second value, the second value being greater in magnitude than the first value;

applying a series of pulses of the signal of a prescribed duration at the second value to the current selected memory cell which has been determined to be shorted.

13. The method of claim 12, wherein an overall duration of the signal to be applied to a selected memory cell during a repair of the memory cell is greater than about half of a duration of a standard read cycle.

14. The method of claim 1, wherein each of the memory cells in the memory circuit comprises a magnetic tunnel junction device.

15. A method for repairing one or more shorted memory cells in a memory circuit, the method comprising the steps of:

setting a signal to be applied to a selected memory cell in the memory circuit to a first value;

setting a current address to a value corresponding to a current selected memory cell in the memory circuit;

reading a logic state of the current selected memory cell with the signal at the first value and determining whether or not the current selected memory cell is shorted;

when the current selected memory cell is determined to be shorted, storing the current address corresponding to the shorted memory cell;

setting the current address to a value corresponding to a new current selected memory cell which has not been previously read, and repeating the steps of reading the logic state of the current selected memory cell and determining whether or not the selected memory cell is shorted;

when at least one address corresponding to a shorted memory cell has been stored, initiating a repair of the shorted memory cell.