Apparatus and method for dynamically repairing a semiconductor memory

• US 20070195623A1
• Filed: 04/24/2007
• Published: 08/23/2007
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Aaron Baum, Brian Callaway
• Original Assignee: Aaron Baum, Brian Callaway
• Inventors: Callaway, Brian, Baum, Aaron
• Granted Patent: US 7,468,922 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.

Claims

1. A method of testing memory for faults, comprising

writing a string of bits to a first collection of memory bits and a second collection of memory bits;

reading a first string of read bits from the first collection of memory bits;

reading a second string of read bits from the second collection of memory bits; and

comparing each bit in the first string of read bits with a corresponding one in the second string of read bits.

2. The method of claim 1, further comprising determining that a fault has occurred in at least one of the first collection of memory bits and the second collection of memory bits when at least one of the first string of read bits differs from a corresponding read bit of the second string of read bits.

3. The method of claim 1, further comprising writing a string of bits to a third collection of memory bits, reading a third string of read bits from the third collection of memory bits and comparing each bit in the second string of read bits with a corresponding bit in the third string of read bits.

4. The method of claim 3, further comprising determining that a fault has occurred in at least one of the second collection of memory bits and the third collection of memory bits when at least one of the second string of read bits differs from a corresponding read bit of the third string of read bits.

5. The method of claim 3, further comprising writing a string of bits to a forth collection of memory bits, reading a forth string of read bits from the forth collection of memory bits and comparing each bit in the third string of read bits with a corresponding bit in the forth string of read bits.

6. The method of claim 5, further comprising determining that a fault has occurred in at least one of the third collection of memory bits and the forth collection of memory bits when at least one of the third string of read bits differs from a corresponding read bit of the forth string of read bits.

7. A method for dynamically testing and repairing a memory, comprising:

testing a plurality of memory segments to identify a faulty memory segment;

identifying an unmapped spare memory segment; and

remapping the spare memory segment to replace the faulty memory segment.

8. The method of claim 7, wherein remapping the spare memory segment comprises permanently remapping the spare memory segment by blowing an antifuse within a semiconductor device.

9. The method of claim 7, wherein remapping the spare memory segment comprises temporarily remapping the spare memory segment by asserting a gate of a MOSFET transistor.

10. The method of claim 7, wherein the testing is performed and controlled by an external source.

11. The method of claim 7, wherein the testing is performed and controlled by an internal built in test circuit.

12. The method of claim 7, wherein the testing, the identifying and temporarily remapping are performed as part of a power up operation of a computer system.

13. A memory including a capability for repairing a faulty collection of memory bits by selecting a spare collection of memory bits to logically replace the faulty collection of memory bits comprising:

a spare collection of memory bits;

a plurality of address bits for controlling a mapping of the spare collection of memory bits to replace the faulty collection of memory bits, wherein a spare memory address bit is one of the plurality of address bits;

a circuit for permanently activating the spare memory address bit; and

a circuit for temporarily activating the spare memory address bit, wherein the spare memory address bit is activated when the spare memory address bit is either permanently activated or temporarily activated.

14. The memory of claim 13, further comprising a circuit in communication with the plurality of address bits for storing faulty memory address locations configured for enabling the spare memory address bits.

15. The memory of claim 13, wherein the memory is a dynamic random access memory fabricated as a semiconductor device.

16. The memory of claim 13, wherein:

the circuit for permanently activating the spare memory address bit comprises an antifuse within a semiconductor device; and

the spare memory address bit is permanently activated by blowing the antifuse.

17. The memory of claim 13, wherein:

the circuit for temporarily activating the spare memory address bit comprises a MOSFET transistor having a gate controlled by a gate signal; and

asserting the gate signal temporarily activates the spare memory address bit.

18. The memory of claim 13, further comprising a memory element for remembering whether the spare memory address bit has been activated.